| commit | 97b60c11ab4cbc42b579d3ebc61d43c69843efb1 | [log] [tgz] |
|---|---|---|
| author | Greg Chadwick <gac@lowrisc.org> | Fri Mar 06 15:20:00 2020 +0000 |
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | Wed Mar 11 12:26:30 2020 +0100 |
| tree | 58e54889d4a03252fe6be1afbb55abd709da3dbe | |
| parent | 442d8db49c7288d37a653ee90c40d54b1bc6f371 [diff] |
Update lowrisc_ibex to lowRISC/ibex@e4b8851 Update code from upstream repository https://github.com/lowRISC/ibex.git to revision e4b8851b4bf056444416dfcb0c91df04ffba74ab * Revert "Re-instate an 0x in dv/uvm/core_ibex/Makefile" (Greg Chadwick) * Merge pull request lowRISC/ibex#624 from ganoam/fpga-opt-perf-mon-pr (Noam Gallmann) * Update google_riscv-dv to google/riscv-dv@4583049 (lowRISC/ibex#660) (taoliug) * Remove stray semicolon (Rupert Swarbrick) * Re-instate an 0x in dv/uvm/core_ibex/Makefile (Rupert Swarbrick) * Fix qrun compile warning (danghai) * [rtl] Break path from data_err_o -> instr_req_o (Greg Chadwick) * [lint] Fix lint waiver (Greg Chadwick) * Add a wrapper script to run a simple_system binary under Spike (Rupert Swarbrick) * Add missing flop to bus error checking in riscv_testutil.sv (Rupert Swarbrick) * Avoid two combinatorial loop warnings in riscv_compliance suite (Rupert Swarbrick) * Fix last verilator warning for ibex_simple_system; add waiver (Rupert Swarbrick) * Simplify the logic in check_ibex_uvm_log (Rupert Swarbrick) * Make ibex_log_to_trace_csv.py PEP8 compliant (Rupert Swarbrick) * Simplify usage of ibex_log_to_trace_csv.py (Rupert Swarbrick) * Allow ibex_log_to_trace_csv.py to run from other directories (Rupert Swarbrick) * Avoid unneccessary rebuilding in dv/uvm/core_ibex/Makefile (Rupert Swarbrick) * Make exiting from simple_system tests work with Spike (Rupert Swarbrick) * Split have_instr definition out of always block in if_stage (Rupert Swarbrick) * Waive verilator warning about unused addr bits in timer.sv (Rupert Swarbrick) * Waive verilator warnings about unused addr bits in simulator_ctrl.sv (Rupert Swarbrick) * Add Verilator waivers to the non-lint target in ibex_core.core (Rupert Swarbrick) * Fix typo in signal declaration in timer.sv (Rupert Swarbrick) * Switch Verilator linter to matches (Stefan Wallentowitz) * [dv] Increase timeouts to fix failures (Greg Chadwick) * [dv] fix qrun compile warnings (lowRISC/ibex#639) (udinator) * Make sim.py less chatty when just compiling the testbench (Rupert Swarbrick) * [dv] remove usage of 0x from sim flow (lowRISC/ibex#638) (udinator) * update riscv_core_setting (lowRISC/ibex#633) (udinator) * Set the ELF entry point in simple system linker script (Rupert Swarbrick) * Improve docs for getting started in verification.rst (Rupert Swarbrick) * Dump to VPD in dv/uvm if Verdi is not available (lowRISC/ibex#630) (Rupert Swarbrick) * Tiny docs fix in examples/simple_system (Rupert Swarbrick) * Fix previous gitignore change for uvm directory rejig (Rupert Swarbrick) * Add .gitignore rules for auto-generated files (Rupert Swarbrick) * Tracer: Mark all functions "automatic" (dawidzim) * Reorganize ibex dv files (lowRISC/ibex#618) (udinator) * VCS compile fix (lowRISC/ibex#616) (udinator) * Update google_riscv-dv to google/riscv-dv@6bd3233 (lowRISC/ibex#617) (udinator) * [doc] Fix reference link (Tobias Wölfel) * CI: Pin riscv-compliance repo to specific commit (Philipp Wagner) * [rtl] Change misa for RV32E (Tobias Wölfel) * [rtl] Alter multdiv to better match style guide (Greg Chadwick) * Doc: Fix broken table in integration docs (Philipp Wagner) * Doc: Documented supported tool versions (Philipp Wagner) * Check for supported tool versions (Philipp Wagner) * Doc: Cleanup Sphinx config file (Philipp Wagner) * [rtl] Add Single Cycle Multiplier targeting FPGA (ganoam) * Reduce latency of slow multiplier (Stefan Mach) * [dv] add command line PMP option configurability (lowRISC/ibex#599) (udinator) * [syn] Fix synthesis script (Greg Chadwick) * [rtl] Fix assertion issues (Greg Chadwick) * Update setuptools and pip to parse more metadata (Philipp Wagner) * [rtl] Introduce default clk/reset to prim_assert (Greg Chadwick) * update testlist typo (lowRISC/ibex#593) (udinator) * Update google_riscv-dv to google/riscv-dv@6e2bc2e (lowRISC/ibex#589) (udinator) * [dv] enable PMP (lowRISC/ibex#588) (udinator) * Update google_riscv-dv to google/riscv-dv@e63c542 (lowRISC/ibex#587) (udinator) Signed-off-by: Greg Chadwick <gac@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can either access it online or build it locally by following the steps below.
$ sudo apt install curl python3 python3-pip $ pip3 install --user -r python-requirements.txt
$ ./util/build_docs.py --preview
This compiles the documentation into ./build/docs and starts a local server, which allows you to access the documentation at http://127.0.0.1:1313.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).