[padring/top] Carry over pinout from bronze and align sim and FPGA tops
Note that this is an intermediate step needed for the pinmux updates.
There are a couple of things that are still Bronze-specific and these
will be cleaned up over the coming weeks as we work towards Silver.
[top] Align englishbreakfast I/O configuration with earlgrey
Since both designs use the same padring, the MIO/DIO config should be
the same, even if not all IOs are connected to a pad.
[topgen] Topgen adjustments to keep MIO order stable
This changes the way the MIOs are enumerated and connected to the
pinmux. Before, topgen would connect all inouts from all modules first,
and then proceed with inputs and outputs.
This is inconsistent with how the ordering is implied by the
`mio_modules` key inside the top hjson.
This fix changes how the MIOs are enumerated. Within a module, topgen
still connects the inouts first, but globally it observes the order
specifiec by the `mio_modules list.
Note that this piece of topgen is going to be overhauled, so this is
just a temporary fix to ensure the MIO insel/outsel indices remain the
same among tops that have different amounts of MIO peripherals.
[top/dv] Alignments and workarounds to get chip simulation working
[top] Regenerate files
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index a5f9ebb..a30b497 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -8,7 +8,6 @@
num_mio_inputs = sum([x["width"] for x in top["pinmux"]["inputs"]])
num_mio_outputs = sum([x["width"] for x in top["pinmux"]["outputs"]])
-num_mio_inouts = sum([x["width"] for x in top["pinmux"]["inouts"]])
num_mio = top["pinmux"]["num_mio"]
num_dio_inputs = sum([x["width"] if x["type"] == "input" else 0 for x in top["pinmux"]["dio"]])
@@ -18,10 +17,10 @@
num_im = sum([x["width"] if "width" in x else 1 for x in top["inter_signal"]["external"]])
-max_miolength = max([len(x["name"]) for x in top["pinmux"]["inputs"] + top["pinmux"]["outputs"] + top["pinmux"]["inouts"]])
+max_miolength = max([len(x["name"]) for x in top["pinmux"]["inputs"] + top["pinmux"]["outputs"]])
max_diolength = max([len(x["name"]) for x in top["pinmux"]["dio"]])
-max_sigwidth = max([x["width"] if "width" in x else 1 for x in top["pinmux"]["inputs"] + top["pinmux"]["outputs"] + top["pinmux"]["inouts"]])
+max_sigwidth = max([x["width"] if "width" in x else 1 for x in top["pinmux"]["inputs"] + top["pinmux"]["outputs"]])
max_sigwidth = len("{}".format(max_sigwidth))
clks_attr = top['clocks']
@@ -111,9 +110,9 @@
import top_${top["name"]}_rnd_cnst_pkg::*;
// Signals
- logic [${num_mio_inputs + num_mio_inouts - 1}:0] mio_p2d;
- logic [${num_mio_outputs + num_mio_inouts - 1}:0] mio_d2p;
- logic [${num_mio_outputs + num_mio_inouts - 1}:0] mio_d2p_en;
+ logic [${num_mio_inputs - 1}:0] mio_p2d;
+ logic [${num_mio_outputs - 1}:0] mio_d2p;
+ logic [${num_mio_outputs - 1}:0] mio_d2p_en;
logic [${num_dio - 1}:0] dio_p2d;
logic [${num_dio - 1}:0] dio_d2p;
logic [${num_dio - 1}:0] dio_d2p_en;
@@ -675,10 +674,10 @@
% endfor
// interrupt assignments
assign intr_vector = {
- % for intr in top["interrupt"][::-1]:
- intr_${intr["name"]},
+ % for k, intr in enumerate(top["interrupt"][::-1]):
+ intr_${intr["name"]}, // ID ${len(top["interrupt"])-k}
% endfor
- 1'b 0 // For ID 0.
+ 1'b 0 // ID 0 is a special case and tied to zero.
};
// TL-UL Crossbar
@@ -709,21 +708,21 @@
% if "pinmux" in top:
// Pinmux connections
- % if num_mio_outputs + num_mio_inouts != 0:
+ % if num_mio_outputs != 0:
assign mio_d2p = {
- % for sig in list(reversed(top["pinmux"]["inouts"] + top["pinmux"]["outputs"])):
+ % for sig in list(reversed(top["pinmux"]["outputs"])):
cio_${sig["name"]}_d2p${"" if loop.last else ","}
% endfor
};
assign mio_d2p_en = {
- % for sig in list(reversed(top["pinmux"]["inouts"] + top["pinmux"]["outputs"])):
+ % for sig in list(reversed(top["pinmux"]["outputs"])):
cio_${sig["name"]}_en_d2p${"" if loop.last else ","}
% endfor
};
% endif
- % if num_mio_inputs + num_mio_inouts != 0:
+ % if num_mio_inputs != 0:
assign {
- % for sig in list(reversed(top["pinmux"]["inouts"] + top["pinmux"]["inputs"])):
+ % for sig in list(reversed(top["pinmux"]["inputs"])):
cio_${sig["name"]}_p2d${"" if loop.last else ","}
% endfor
} = mio_p2d;
