[edn/csrng] change REGWEN to be module enable based Signed-off-by: Mark Branstad <mark.branstad@wdc.com>

diff --git a/hw/ip/csrng/rtl/csrng_block_encrypt.sv b/hw/ip/csrng/rtl/csrng_block_encrypt.sv
index f3aac3a..5291409 100644
--- a/hw/ip/csrng/rtl/csrng_block_encrypt.sv
+++ b/hw/ip/csrng/rtl/csrng_block_encrypt.sv

@@ -166,7 +166,6 @@
   assign block_encrypt_id_o = sfifo_blkenc_id;
   assign block_encrypt_v_o = !aes_cipher_core_enable ? sfifo_blkenc_v : cipher_data_out;
   assign cipher_out_ready =
-         (!block_encrypt_enable_i) ? aes_pkg::SP2V_HIGH : // flush out AES in halt case
          block_encrypt_rdy_i ? aes_pkg::SP2V_HIGH :
          aes_pkg::SP2V_LOW;
 

diff --git a/hw/ip/csrng/rtl/csrng_core.sv b/hw/ip/csrng/rtl/csrng_core.sv
index 84252f3..9d73239 100644
--- a/hw/ip/csrng/rtl/csrng_core.sv
+++ b/hw/ip/csrng/rtl/csrng_core.sv

@@ -1359,7 +1359,6 @@
 
   // es to cs halt request to reduce power spikes
   assign cs_aes_halt_d =
-         (!cs_enable) ? '0 :
          (ctr_drbg_upd_es_ack && ctr_drbg_gen_es_ack && block_encrypt_quiet);
 
   assign cs_aes_halt_o.cs_aes_halt_ack = cs_aes_halt_q;

diff --git a/hw/ip/csrng/rtl/csrng_main_sm.sv b/hw/ip/csrng/rtl/csrng_main_sm.sv
index c8fc938..a129a03 100644
--- a/hw/ip/csrng/rtl/csrng_main_sm.sv
+++ b/hw/ip/csrng/rtl/csrng_main_sm.sv

@@ -101,90 +101,132 @@
     main_sm_err_o = 1'b0;
     unique case (state_q)
       Idle: begin
-        if (halt_main_sm_i) begin
-          state_d = SMHalted;
-        end else begin
-          if (ctr_drbg_cmd_req_rdy_i) begin
-            if (acmd_avail_i) begin
-              acmd_accept_o = 1'b1;
-              if (acmd_i == INS) begin
-                if (acmd_eop_i) begin
+        if (enable_i) begin
+          if (halt_main_sm_i) begin
+            state_d = SMHalted;
+          end else begin
+            if (ctr_drbg_cmd_req_rdy_i) begin
+              if (acmd_avail_i) begin
+                acmd_accept_o = 1'b1;
+                if (acmd_i == INS) begin
+                  if (acmd_eop_i) begin
+                    acmd_hdr_capt_o = 1'b1;
+                    state_d = InstantPrep;
+                  end
+                end else if (acmd_i == RES) begin
+                  if (acmd_eop_i) begin
+                    acmd_hdr_capt_o = 1'b1;
+                    state_d = ReseedPrep;
+                  end
+                end else if (acmd_i == GEN) begin
                   acmd_hdr_capt_o = 1'b1;
-                  state_d = InstantPrep;
-                end
-              end else if (acmd_i == RES) begin
-                if (acmd_eop_i) begin
+                  state_d = GenerateReq;
+                end else if (acmd_i == UPD) begin
+                  if (acmd_eop_i) begin
+                    acmd_hdr_capt_o = 1'b1;
+                    state_d = UpdatePrep;
+                  end
+                end else if (acmd_i == UNI) begin
                   acmd_hdr_capt_o = 1'b1;
-                  state_d = ReseedPrep;
+                  state_d = UninstantReq;
                 end
-              end else if (acmd_i == GEN) begin
-                acmd_hdr_capt_o = 1'b1;
-                state_d = GenerateReq;
-              end else if (acmd_i == UPD) begin
-                if (acmd_eop_i) begin
-                  acmd_hdr_capt_o = 1'b1;
-                  state_d = UpdatePrep;
-                end
-              end else if (acmd_i == UNI) begin
-                acmd_hdr_capt_o = 1'b1;
-                state_d = UninstantReq;
               end
             end
           end
         end
       end
       InstantPrep: begin
-        if (flag0_i) begin
-          // assumes all adata is present now
-          state_d = InstantReq;
+        if (!enable_i) begin
+          state_d = Idle;
         end else begin
-          // delay one clock to fix timing issue
-          cmd_entropy_req_o = 1'b1;
-          if (cmd_entropy_avail_i) begin
+          if (flag0_i) begin
+            // assumes all adata is present now
             state_d = InstantReq;
+          end else begin
+          // delay one clock to fix timing issue
+            cmd_entropy_req_o = 1'b1;
+            if (cmd_entropy_avail_i) begin
+              state_d = InstantReq;
+            end
           end
         end
       end
       InstantReq: begin
-        instant_req_o = 1'b1;
-        state_d = CmdCompWait;
+        if (!enable_i) begin
+          state_d = Idle;
+        end else begin
+          instant_req_o = 1'b1;
+          state_d = CmdCompWait;
+        end
       end
       ReseedPrep: begin
-        cmd_entropy_req_o = 1'b1;
-        // assumes all adata is present now
-        if (cmd_entropy_avail_i) begin
-          state_d = ReseedReq;
+        if (!enable_i) begin
+          state_d = Idle;
+        end else begin
+          cmd_entropy_req_o = 1'b1;
+          // assumes all adata is present now
+          if (cmd_entropy_avail_i) begin
+            state_d = ReseedReq;
+          end
         end
       end
       ReseedReq: begin
-        reseed_req_o = 1'b1;
-        state_d = CmdCompWait;
+        if (!enable_i) begin
+          state_d = Idle;
+        end else begin
+          reseed_req_o = 1'b1;
+          state_d = CmdCompWait;
+        end
       end
       GenerateReq: begin
-        generate_req_o = 1'b1;
-        state_d = CmdCompWait;
+        if (!enable_i) begin
+          state_d = Idle;
+        end else begin
+          generate_req_o = 1'b1;
+          state_d = CmdCompWait;
+        end
       end
       UpdatePrep: begin
-        // assumes all adata is present now
-        state_d = UpdateReq;
+        if (!enable_i) begin
+          state_d = Idle;
+        end else begin
+          // assumes all adata is present now
+          state_d = UpdateReq;
+        end
       end
       UpdateReq: begin
-        update_req_o = 1'b1;
-        state_d = CmdCompWait;
+        if (!enable_i) begin
+          state_d = Idle;
+        end else begin
+          update_req_o = 1'b1;
+          state_d = CmdCompWait;
+        end
       end
       UninstantReq: begin
-        uninstant_req_o = 1'b1;
-        state_d = CmdCompWait;
+        if (!enable_i) begin
+          state_d = Idle;
+        end else begin
+          uninstant_req_o = 1'b1;
+          state_d = CmdCompWait;
+        end
       end
       CmdCompWait: begin
-        if (cmd_complete_i) begin
+        if (!enable_i) begin
           state_d = Idle;
+        end else begin
+          if (cmd_complete_i) begin
+            state_d = Idle;
+          end
         end
       end
       SMHalted: begin
-        main_sm_halted_o = 1'b1;
-        if (!halt_main_sm_i) begin
+        if (!enable_i) begin
           state_d = Idle;
+        end else begin
+          main_sm_halted_o = 1'b1;
+          if (!halt_main_sm_i) begin
+            state_d = Idle;
+          end
         end
       end
       Error: begin
@@ -192,10 +234,6 @@
       end
       default: state_d = Error;
     endcase
-    // Master override for FSM
-    if (!enable_i) begin
-      state_d = Idle;
-    end
   end
 
 endmodule

diff --git a/hw/ip/csrng/rtl/csrng_state_db.sv b/hw/ip/csrng/rtl/csrng_state_db.sv
index 2cd40a2..30ec6a5 100644
--- a/hw/ip/csrng/rtl/csrng_state_db.sv
+++ b/hw/ip/csrng/rtl/csrng_state_db.sv

@@ -51,6 +51,7 @@
   localparam int InternalStateWidth = 2+KeyLen+BlkLen+CtrLen;
   localparam int RegInternalStateWidth = 30+InternalStateWidth;
   localparam int RegW = 32;
+  localparam int StateWidth = 1+1+KeyLen+BlkLen+CtrLen+StateId+1;
 
   logic [StateId-1:0]              state_db_id;
   logic [KeyLen-1:0]               state_db_key;
@@ -170,7 +171,8 @@
   assign {state_db_fips,state_db_inst_st,
           state_db_key,
           state_db_v,state_db_rc,
-          state_db_id,state_db_sts} = {state_db_wr_fips_i,instance_status,
+          state_db_id,state_db_sts} = {StateWidth{state_db_enable_i}} &
+                                      {state_db_wr_fips_i,instance_status,
                                        state_db_wr_key_i,
                                        state_db_wr_v_i,state_db_wr_res_ctr_i,
                                        state_db_wr_inst_id_i,state_db_wr_sts_i};
@@ -184,15 +186,12 @@
   assign state_db_write = state_db_enable_i && state_db_wr_req_i;
 
   assign state_db_sts_ack_d =
-         (!state_db_enable_i) ? '0 :
          state_db_write;
 
   assign state_db_sts_sts_d =
-         (!state_db_enable_i) ? '0 :
          state_db_sts;
 
   assign state_db_sts_id_d =
-         (!state_db_enable_i) ? '0 :
          state_db_id;
 
   assign state_db_sts_ack_o = state_db_sts_ack_q;

diff --git a/hw/ip/entropy_src/data/entropy_src.hjson b/hw/ip/entropy_src/data/entropy_src.hjson
index 5513617..839a2dc 100644
--- a/hw/ip/entropy_src/data/entropy_src.hjson
+++ b/hw/ip/entropy_src/data/entropy_src.hjson

@@ -73,8 +73,7 @@
         {
             bits: "0",
             desc: ''' When true, all writeable registers can be modified.
-            When false, they become read-only. Defaults true, write one to clear. Note that this needs to be
-            cleared after initial configuration at boot in order to lock in the listed register settings.
+            When false, they become read-only.
             '''
             resval: 1
         }