commit b30114e8b68f9fd2c5e14e232632dcb635cdb518
author Cindy Chen <chencindy@google.com> Wed Nov 25 14:41:12 2020 -0800
committer cindychip <cindy.chen0316@gmail.com> Mon Nov 30 13:52:06 2020 -0800
tree 8fbc3d1830dbb7388848efaad2e4b576dbd158da
parent 47b9a1b320f644510bc933c188f2e37bc55011f1

[dv/lc_ctrl] initial dv testbench for LC

This PR:
1. Add a dv testbench for LC using uvmdvgen.
2. Add pins to trigger LC init.
3. Add LC testplan in build_doc.py
4. Add a lc_ctrl_if to drive input of lc

Signed-off-by: Cindy Chen <chencindy@google.com>

util/build_docs.py

diff --git a/util/build_docs.py b/util/build_docs.py
index 6a1bcb2..e9f065e 100755
--- a/util/build_docs.py
+++ b/util/build_docs.py
@@ -99,6 +99,7 @@
         "hw/ip/hmac/data/hmac_testplan.hjson",
         "hw/ip/i2c/data/i2c_testplan.hjson",
         "hw/ip/keymgr/data/keymgr_testplan.hjson",
+        "hw/ip/lc_ctrl/data/lc_ctrl_testplan.hjson",
         "hw/ip/otp_ctrl/data/otp_ctrl_testplan.hjson",
         "hw/ip/padctrl/data/padctrl_fpv_testplan.hjson",
         "hw/ip/pattgen/data/pattgen_testplan.hjson",