[dv] Update tl_agent to use bus_params_pkg
Replaces parameters from top_pkg with parameters from bus_params_pkg.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/dv/sv/tl_agent/seq_lib/tl_host_single_seq.sv b/hw/dv/sv/tl_agent/seq_lib/tl_host_single_seq.sv
index 2975204..5ab2183 100644
--- a/hw/dv/sv/tl_agent/seq_lib/tl_host_single_seq.sv
+++ b/hw/dv/sv/tl_agent/seq_lib/tl_host_single_seq.sv
@@ -4,13 +4,13 @@
// Extend host seq to send single specific item constructed by the caller
class tl_host_single_seq extends tl_host_seq;
- rand bit write;
- rand bit [top_pkg::TL_AW-1:0] addr;
- rand bit [OpcodeWidth-1:0] opcode;
- rand bit [top_pkg::TL_SZW-1:0] size;
- rand bit [top_pkg::TL_AIW-1:0] source;
- rand bit [top_pkg::TL_DBW-1:0] mask;
- rand bit [top_pkg::TL_DW-1:0] data;
+ rand bit write;
+ rand bit [AddrWidth-1:0] addr;
+ rand bit [OpcodeWidth-1:0] opcode;
+ rand bit [SizeWidth-1:0] size;
+ rand bit [SourceWidth-1:0] source;
+ rand bit [MaskWidth-1:0] mask;
+ rand bit [DataWidth-1:0] data;
// for most cases, upper seq just needs to provide addr[$:2], data, mask value, write.
// addr[1:0]/size/source/opcode can be randomized in tl_seq_item based on mask value
@@ -29,10 +29,10 @@
a_valid_delay inside {[min_req_delay:max_req_delay]};
a_data == data;
a_mask == mask;
- a_addr[top_pkg::TL_AW-1:2] == addr[top_pkg::TL_AW-1:2];
- control_addr_alignment -> a_addr[1:0] == addr[1:0];
- control_rand_size -> a_size == size;
- control_rand_source -> a_source == source;
+ a_addr[AddrWidth-1:2] == addr[AddrWidth-1:2];
+ control_addr_alignment -> a_addr[1:0] == addr[1:0];
+ control_rand_size -> a_size == size;
+ control_rand_source -> a_source == source;
if (control_rand_opcode) {
a_opcode == opcode;
} else {
diff --git a/hw/dv/sv/tl_agent/tl_agent.core b/hw/dv/sv/tl_agent/tl_agent.core
index 31186ed..2773d7f 100644
--- a/hw/dv/sv/tl_agent/tl_agent.core
+++ b/hw/dv/sv/tl_agent/tl_agent.core
@@ -11,6 +11,7 @@
- lowrisc:tlul:headers:0.1
- lowrisc:dv:mem_model
- lowrisc:dv:dv_lib
+ - lowrisc:opentitan:bus_params_pkg
files:
- tl_if.sv
- tl_agent_pkg.sv
diff --git a/hw/dv/sv/tl_agent/tl_agent_pkg.sv b/hw/dv/sv/tl_agent/tl_agent_pkg.sv
index 6279359..1deffd4 100644
--- a/hw/dv/sv/tl_agent/tl_agent_pkg.sv
+++ b/hw/dv/sv/tl_agent/tl_agent_pkg.sv
@@ -6,7 +6,7 @@
package tl_agent_pkg;
// dep packages
import uvm_pkg::*;
- import top_pkg::*;
+ import bus_params_pkg::*;
import tlul_pkg::*;
import mem_model_pkg::*;
import dv_lib_pkg::*;
@@ -16,12 +16,12 @@
`include "uvm_macros.svh"
`include "dv_macros.svh"
- parameter int AddrWidth = top_pkg::TL_AW;
- parameter int DataWidth = top_pkg::TL_DW;
- parameter int SizeWidth = top_pkg::TL_SZW;
- parameter int MaskWidth = top_pkg::TL_DBW;
- parameter int SourceWidth = top_pkg::TL_AIW;
- parameter int DUserWidth = top_pkg::TL_DUW;
+ parameter int AddrWidth = bus_params_pkg::BUS_AW;
+ parameter int DataWidth = bus_params_pkg::BUS_DW;
+ parameter int SizeWidth = bus_params_pkg::BUS_SZW;
+ parameter int MaskWidth = bus_params_pkg::BUS_DBW;
+ parameter int SourceWidth = bus_params_pkg::BUS_AIW;
+ parameter int DUserWidth = bus_params_pkg::BUS_DUW;
parameter int OpcodeWidth = 3;
typedef class tl_seq_item;
diff --git a/hw/dv/sv/tl_agent/tl_reg_adapter.sv b/hw/dv/sv/tl_agent/tl_reg_adapter.sv
index 9af3cb7..8a4ffac 100644
--- a/hw/dv/sv/tl_agent/tl_reg_adapter.sv
+++ b/hw/dv/sv/tl_agent/tl_reg_adapter.sv
@@ -29,18 +29,18 @@
if (rw.kind == UVM_READ) begin
if (rw.byte_en == '1 && item.element_kind == UVM_REG) begin // csr full read
`DV_CHECK_RANDOMIZE_WITH_FATAL(bus_item_loc,
- a_opcode == tlul_pkg::Get;
- a_addr[TL_AW-1:2] == rw.addr[TL_AW-1:2];
- $countones(a_mask) dist {TL_DBW :/ 1,
- [0:TL_DBW-1] :/ 1};)
+ a_opcode == tlul_pkg::Get;
+ a_addr[AddrWidth-1:2] == rw.addr[AddrWidth-1:2];
+ $countones(a_mask) dist {MaskWidth :/ 1,
+ [0:MaskWidth-1] :/ 1};)
end else begin // csr field read
`DV_CHECK_RANDOMIZE_WITH_FATAL(bus_item_loc,
- a_opcode == tlul_pkg::Get;
- a_addr[TL_AW-1:2] == rw.addr[TL_AW-1:2];
- a_mask == rw.byte_en;)
+ a_opcode == tlul_pkg::Get;
+ a_addr[AddrWidth-1:2] == rw.addr[AddrWidth-1:2];
+ a_mask == rw.byte_en;)
end
end else begin // randomize CSR partial or full write
- // Actual width of the CSR may be < TL_DW bits depending on fields and their widths
+ // Actual width of the CSR may be < DataWidth bits depending on fields and their widths
// In that case, the transaction size in bytes and partial write mask need to be at least as
// wide as the CSR to be a valid transaction. Otherwise, the DUT can return an error response
int msb;
@@ -52,7 +52,7 @@
`DV_CHECK_FATAL($cast(csr, rg))
msb = csr.get_msb_pos();
end else if (item.element_kind == UVM_MEM) begin
- msb = TL_DW - 1;
+ msb = DataWidth - 1;
end else begin
`uvm_fatal(`gfn, $sformatf("Unexpected address 0x%0h", rw.addr))
end
