sw/vendor/patches/riscv_compliance/0002-Remove-specific-tests-that-do-not-pass-on-ibex.patch

From d57e5fa67c1b27a5812b0b1c63c406e2eb65e44b Mon Sep 17 00:00:00 2001
From: Timothy Chen <timothytim@google.com>
Date: Thu, 7 Nov 2019 21:54:13 -0800
Subject: [PATCH 2/2] Remove specific tests that do not pass on ibex.

When FENCE.I is implemented in the future, add these tests back.

Signed-off-by: Timothy Chen <timothytim@google.com>
---
 riscv-target/opentitan/README.md              | 92 ++++++-------------
 riscv-target/opentitan/compliance_test.h      |  2 +-
 .../opentitan/device/rv32imc/Makefile.include | 68 +++++++-------
 riscv-target/opentitan/device/rv32imc/link.ld | 33 +++----
 .../opentitan/device/rv32imc/platform.yaml    |  6 +-
 riscv-target/opentitan/device/rv32imc/wrap.c  |  5 +-
 riscv-test-suite/rv32i/Makefrag               | 21 +++--
 7 files changed, 96 insertions(+), 131 deletions(-)

diff --git a/riscv-target/opentitan/README.md b/riscv-target/opentitan/README.md
index 7fceaae..bca8749 100644
--- a/riscv-target/opentitan/README.md
+++ b/riscv-target/opentitan/README.md
@@ -1,15 +1,15 @@
----
-title: "OpenTitan RISC-V Compliance Testing"
----
 
 # Overview
-The RISC-V compliance test can be run on either FPGA or Verilator.
+The RISC-V compliance test can be run on either OpenTitan FPGA or Verilator.
+OpenTitan is an open source project to build transparent, high-quality reference designs for silicon root of trust chips.
+Please see the [OpenTitan website](https://opentitan.org) for more details.
+
 To run on Verilator, set the variables below
 
 ```console
 $ export RISCV_TARGET=opentitan
 $ export RISCV_DEVICE=rv32imc
-$ export TARGET=verilator
+$ export OPENTITAN_TARGET=verilator
 ```
 
 To run on FPGA, set the variables below.
@@ -18,31 +18,30 @@ The `FPGA_UART` variable must be set to wherever a valid device is connected.
 ```console
 $ export RISCV_TARGET=opentitan
 $ export RISCV_DEVICE=rv32imc
-$ export TARGET=fpga
-$ export FPGA_UART=/dev/tty*
+$ export OT_TARGET=fpga
+$ export OT_FPGA_UART=/dev/tty*
 ```
 
 By default, the test assumes there exists a valid Verilator build at `${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`.
 If your Verilator build is at a different location, please set that as well when running with Verilator.
-For instructions on how to create a Verilator build, please refer to the [Verilator guide]({{< relref "doc/ug/getting_started_verilator" >}}).
 
 ```console
 $ export TARGET_SIM=${PATH_TO_VERILATOR_BUILD}
 ```
 
 When running against FPGA, the test assumes the FPGA is already programmed and ready to go.
-To find out how to properly build and flash FPGA, please refer to the [FPGA manual]({{< relref "doc/rm/ref_manual_fpga" >}})
+To quickly get started with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/)
 
 
-Now, run the tests.
+Now, run the tests from the riscv_compliance directory.
 The following output will be seen (software build steps are truncated).
 The example below uses Verilator as an example, but the FPGA output is nearly identical.
 
 ```console
-$ cd $REPO_TOP
-$ make -C sw/vendor/riscv_compliance RISCV_ISA=rv32i \
-  && make -C sw/vendor/riscv_compliance RISCV_ISA=rv32im \
-  && make -C sw/vendor/riscv_compliance RISCV_ISA=rv32imc
+$ cd $RISCV_COMPLIANCE_REPO_BASE
+$ make RISCV_ISA=rv32i \
+  && make RISCV_ISA=rv32im \
+  && make RISCV_ISA=rv32imc
 
 
 Rom initialized with program at $REPO_TOP/sw/vendor/riscv_compliance/../../boot_rom/rom.vmem
@@ -77,59 +76,22 @@ Check         I-ADD-01 ... OK
 Check        I-ADDI-01 ... OK
 Check         I-AND-01 ... OK
 Check        I-ANDI-01 ... OK
-Check       I-AUIPC-01 ... OK
-Check         I-BEQ-01 ... OK
-Check         I-BGE-01 ... OK
-Check        I-BGEU-01 ... OK
-Check         I-BLT-01 ... OK
-Check        I-BLTU-01 ... OK
-Check         I-BNE-01 ... OK
-Check       I-CSRRC-01 ... OK
-Check      I-CSRRCI-01 ... OK
-Check       I-CSRRS-01 ... OK
-Check      I-CSRRSI-01 ... OK
-Check       I-CSRRW-01 ... OK
-Check      I-CSRRWI-01 ... OK
-Check I-DELAY_SLOTS-01 ... OK
-Check      I-EBREAK-01 ... OK
-Check       I-ECALL-01 ... OK
-Check   I-ENDIANESS-01 ... OK
-Check     I-FENCE.I-01 ... OK
-Check             I-IO ... OK
-Check         I-JAL-01 ... OK
-Check        I-JALR-01 ... OK
-Check          I-LB-01 ... OK
-Check         I-LBU-01 ... OK
-Check          I-LH-01 ... OK
-Check         I-LHU-01 ... OK
-Check         I-LUI-01 ... OK
-Check          I-LW-01 ... OK
-Check I-MISALIGN_JMP-01 ... OK
-Check I-MISALIGN_LDST-01 ... OK
-Check         I-NOP-01 ... OK
-Check          I-OR-01 ... OK
-Check         I-ORI-01 ... OK
-Check     I-RF_size-01 ... OK
-Check    I-RF_width-01 ... OK
-Check       I-RF_x0-01 ... OK
-Check          I-SB-01 ... OK
-Check          I-SH-01 ... OK
-Check         I-SLL-01 ... OK
-Check        I-SLLI-01 ... OK
-Check         I-SLT-01 ... OK
-Check        I-SLTI-01 ... OK
-Check       I-SLTIU-01 ... OK
-Check        I-SLTU-01 ... OK
-Check         I-SRA-01 ... OK
-Check        I-SRAI-01 ... OK
-Check         I-SRL-01 ... OK
-Check        I-SRLI-01 ... OK
-Check         I-SUB-01 ... OK
-Check          I-SW-01 ... OK
-Check         I-XOR-01 ... OK
-Check        I-XORI-01 ... OK
+
+...
+
 --------------------------------
 OK: 55/55
 
 
 ```
+
+
+## Removed Tests
+A small number of tests are not run for OpenTitan riscv_compliance since the underlying core does not yet support specific features.
+The removed tests are the following:
+
+* I-MISALIGN_JMP-01
+* I-MISALIGN_LDST-01
+* I-FENCE.I-01
+* I-ECALL-01
+* I-EBREAK-01
diff --git a/riscv-target/opentitan/compliance_test.h b/riscv-target/opentitan/compliance_test.h
index 7f1bdd3..5d56101 100644
--- a/riscv-target/opentitan/compliance_test.h
+++ b/riscv-target/opentitan/compliance_test.h
@@ -7,7 +7,7 @@
 #ifndef _COMPLIANCE_TEST_H
 #define _COMPLIANCE_TEST_H
 
-#include "sw/vendor/riscv_compliance/riscv-test-env/p/riscv_test.h"
+#include "riscv_test.h"
 
 //-----------------------------------------------------------------------
 // RV Compliance Macros
diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include
index c18820f..6b32d29 100644
--- a/riscv-target/opentitan/device/rv32imc/Makefile.include
+++ b/riscv-target/opentitan/device/rv32imc/Makefile.include
@@ -1,29 +1,28 @@
-## Copyright lowRISC contributors.
-## Licensed under the Apache License, Version 2.0, see LICENSE for details.
-## SPDX-License-Identifier: Apache-2.0
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
 
+OPENTITAN     = $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device/rv32imc
+OT_SW         = $(ROOTDIR)/../../device
+OT_ROOT       = $(OT_SW)/../../
+OT_TOOLS     ?= /tools/riscv/bin
+OT_FPGA_UART ?=
+OT_TARGET    ?= fpga
+LDSCRIPT      = $(OPENTITAN)/link.ld
+TRAPHANDLER   = $(OPENTITAN)/handler.S
+DEFINES       = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DTRAPHANDLER="\"$(TRAPHANDLER)\""
+TARGET_SIM   ?= $(OT_ROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator
 
-OT           = $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device/rv32imc
-OTSW         = $(ROOTDIR)/../../device
-OTROOT       = $(OTSW)/../../
-LDSCRIPT     = $(OT)/link.ld
-TRAPHANDLER  = $(OT)/handler.S
-DEFINES      = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DTRAPHANDLER="\"$(TRAPHANDLER)\""
-RV_TOOLS    ?= /tools/riscv/bin
-FPGA_UART   ?=
-TARGET_SIM  ?= $(OTROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator
-TARGET      ?= fpga
-
-ifeq ($(TARGET),fpga)
+ifeq ($(OT_TARGET),fpga)
 	CARG =
 	MAKEARG =
-	PYTEST_OPT = --fpga_uart $(FPGA_UART) --spiflash $(OTROOT)/sw/host/spiflash/spiflash \
+	PYTEST_OPT = --fpga_uart $(OT_FPGA_UART) --spiflash $(OT_ROOT)/sw/host/spiflash/spiflash \
 		--test_bin $(work_dir_isa)/$<.bin
 else
 	CARG = -DSIMULATION=1
 	MAKEARG = SIM=1
 	PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(work_dir_isa)/$<.vmem \
-		--rom_bin $(OTSW)/boot_rom/rom.vmem
+		--rom_bin $(OT_SW)/boot_rom/rom.vmem
 endif
 
 
@@ -32,7 +31,7 @@ endif
 # Parse the resulting log for the output signatures
 # Convert all signatures to lower case since the reference is in all lower case
 RUN_TARGET=\
-        pytest -s -v $(OTROOT)/test/systemtest/functional_$(TARGET)_test.py \
+        pytest -s -v $(OT_ROOT)/test/systemtest/functional_$(OT_TARGET)_test.py \
         $(PYTEST_OPT) \
         --log $(work_dir_isa)/$<.uart.log; \
         grep -o 'SIG: [a-zA-Z0-9_]*' $(work_dir_isa)/$<.uart.log | sed 's/SIG: //' \
@@ -40,12 +39,12 @@ RUN_TARGET=\
         tr '[:upper:]' '[:lower:]' < $(work_dir_isa)/$(*).signature.temp.output > $(work_dir_isa)/$(*).signature.output;
 
 
-RISCV_PREFIX   ?= ${RV_TOOLS}/riscv32-unknown-elf-
-RISCV_GCC      ?= ${RV_TOOLS}/riscv32-unknown-elf-gcc
-RISCV_OBJDUMP  ?= ${RV_TOOLS}/riscv32-unknown-elf-objdump
-RISCV_OBJCOPY  ?= ${RV_TOOLS}/riscv32-unknown-elf-objcopy
-RISCV_NM       ?= ${RV_TOOLS}/riscv32-unknown-elf-nm
-RISCV_READELF  ?= ${RV_TOOLS}/riscv32-unknown-elf-readelf
+RISCV_PREFIX   ?= ${OT_TOOLS}/riscv32-unknown-elf-
+RISCV_GCC      ?= ${OT_TOOLS}/riscv32-unknown-elf-gcc
+RISCV_OBJDUMP  ?= ${OT_TOOLS}/riscv32-unknown-elf-objdump
+RISCV_OBJCOPY  ?= ${OT_TOOLS}/riscv32-unknown-elf-objcopy
+RISCV_NM       ?= ${OT_TOOLS}/riscv32-unknown-elf-nm
+RISCV_READELF  ?= ${OT_TOOLS}/riscv32-unknown-elf-readelf
 RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g
 
 
@@ -55,22 +54,21 @@ RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostart
 # After the libraries are built, the necessary collateral (vmem for verilator, bin
 # for fpga) are created
 COMPILE_TARGET=\
-        make -C $$(OTSW) SW_DIR=boot_rom $(MAKEARG) clean all; \
+        make -C $$(OT_SW) SW_DIR=boot_rom $(MAKEARG) RV_TOOLS=$(OT_TOOLS) clean all; \
 	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
 		-I$(ROOTDIR)/riscv-test-env/ \
 		-I$(ROOTDIR)/riscv-test-env/p/ \
-                -I$(OTSW)/boot_rom/lib \
-                -I$(OTSW)/lib \
-                -I$(OTROOT) \
+                -I$(OT_SW)/boot_rom/lib \
+                -I$(OT_SW)/lib \
 		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
 		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
 		$(DEFINES) -T$(LDSCRIPT) $$< \
-                $(OT)/wrap.c \
-                -L$(OTSW)/boot_rom/lib \
+                $(OPENTITAN)/wrap.c \
+                -L$(OT_SW)/boot_rom/lib \
                 -lot \
 		-o $(work_dir_isa)/$$@; \
-    $$(RISCV_OBJDUMP) -SD $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \
-    $$(RISCV_READELF) -a $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.readelf; \
-    $$(RISCV_NM) $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.nm; \
-    $$(RISCV_OBJCOPY) -O binary $(work_dir_isa)/$$@ $(work_dir_isa)/$$@.bin; \
-    srec_cat $(work_dir_isa)/$$@.bin -binary -offset 0x0000 -byte-swap 4 -o $(work_dir_isa)/$$@.vmem -vmem
+        $$(RISCV_OBJDUMP) -SD $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \
+        $$(RISCV_READELF) -a $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.readelf; \
+        $$(RISCV_NM) $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.nm; \
+        $$(RISCV_OBJCOPY) -O binary $(work_dir_isa)/$$@ $(work_dir_isa)/$$@.bin; \
+        srec_cat $(work_dir_isa)/$$@.bin -binary -offset 0x0000 -byte-swap 4 -o $(work_dir_isa)/$$@.vmem -vmem
diff --git a/riscv-target/opentitan/device/rv32imc/link.ld b/riscv-target/opentitan/device/rv32imc/link.ld
index 9259121..2ae1f1c 100644
--- a/riscv-target/opentitan/device/rv32imc/link.ld
+++ b/riscv-target/opentitan/device/rv32imc/link.ld
@@ -3,19 +3,19 @@
    SPDX-License-Identifier: Apache-2.0
 */
 
-OUTPUT_ARCH( "riscv" )
+OUTPUT_ARCH("riscv")
 ENTRY(_start)
 
 /* required to correctly link newlib */
-GROUP( -lc -lgloss -lgcc -lsupc++ )
+GROUP(-lc -lgloss -lgcc -lsupc++)
 
 SEARCH_DIR(.)
 __DYNAMIC  =  0;
 
 MEMORY
 {
-    flash (rx)     : ORIGIN = 0x20000000, LENGTH = 0x100000
-    ram (wx)      : ORIGIN = 0x10000000, LENGTH = 0x10000
+    flash (rx) : ORIGIN = 0x20000000, LENGTH = 0x100000
+    ram (wx)   : ORIGIN = 0x10000000, LENGTH = 0x10000
 }
 
 _stack_start = ORIGIN(ram) + LENGTH(ram);
@@ -24,32 +24,33 @@ _stack_start = ORIGIN(ram) + LENGTH(ram);
 SECTIONS
 {
   .text.init ORIGIN(flash) : {
-             *(.text.init)
+    *(.text.init)
   } > flash
 
   .text.trap : {
-        . = ALIGN(0x100);
-        *(.text.trap)
+    . = ALIGN(0x100);
+    *(.text.trap)
   } > flash
 
   .text : {
-        . = ALIGN(0x100);
-        *(.text)
+    . = ALIGN(0x100);
+    *(.text)
   } > flash
 
   .data : {
-        . = ALIGN(0x100);
-        *(.data.*)
+    . = ALIGN(0x100);
+    *(.data.*)
   } > flash
 
   .tohost ORIGIN(ram) (NOLOAD) : {
-        *(.tohost)
-        *(.test.output)
-   } > ram
+    *(.tohost)
+    *(.test.output)
+  } > ram
 
   .bss : {
-        . = ALIGN(0x100);
-        *(.bss)
+    . = ALIGN(0x100);
+    *(.bss)
   } > ram
+
   _end = .;
 }
diff --git a/riscv-target/opentitan/device/rv32imc/platform.yaml b/riscv-target/opentitan/device/rv32imc/platform.yaml
index e834efb..7d547d9 100644
--- a/riscv-target/opentitan/device/rv32imc/platform.yaml
+++ b/riscv-target/opentitan/device/rv32imc/platform.yaml
@@ -1,6 +1,6 @@
-## Copyright lowRISC contributors.
-## Licensed under the Apache License, Version 2.0, see LICENSE for details.
-## SPDX-License-Identifier: Apache-2.0
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
 
 mtime:
   implemented: False
diff --git a/riscv-target/opentitan/device/rv32imc/wrap.c b/riscv-target/opentitan/device/rv32imc/wrap.c
index 5834199..37e2224 100644
--- a/riscv-target/opentitan/device/rv32imc/wrap.c
+++ b/riscv-target/opentitan/device/rv32imc/wrap.c
@@ -8,10 +8,11 @@
 #include "uart.h"
 
 #define SIM_TERM_ADDR 0x10008000
+extern uint32_t begin_signature[];
+extern uint32_t end_signature[];
 
 void dump_signature(void) {
-  extern uint32_t begin_signature[];
-  extern uint32_t end_signature[];
+
 
   uint32_t size = end_signature - begin_signature;
   uart_init(UART_BAUD_RATE);
diff --git a/riscv-test-suite/rv32i/Makefrag b/riscv-test-suite/rv32i/Makefrag
index 4334916..9e5991b 100644
--- a/riscv-test-suite/rv32i/Makefrag
+++ b/riscv-test-suite/rv32i/Makefrag
@@ -2,7 +2,7 @@
 #
 # Copyright (c) 2017, Codasip Ltd.
 # All rights reserved.
-# 
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are met:
 #      * Redistributions of source code must retain the above copyright
@@ -13,8 +13,8 @@
 #      * Neither the name of the Codasip Ltd. nor the
 #        names of its contributors may be used to endorse or promote products
 #        derived from this software without specific prior written permission.
-# 
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
@@ -22,7 +22,7 @@
 # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Description: Makefrag for RV32I compliance tests
@@ -32,8 +32,6 @@ rv32i_sc_tests = \
     I-RF_x0-01 \
     I-RF_size-01 \
     I-RF_width-01 \
-    I-MISALIGN_JMP-01 \
-    I-MISALIGN_LDST-01 \
     I-DELAY_SLOTS-01 \
     I-JAL-01 \
     I-JALR-01 \
@@ -56,7 +54,6 @@ rv32i_sc_tests = \
     I-XOR-01 \
     I-SUB-01 \
     I-ANDI-01 \
-    I-FENCE.I-01 \
     I-SLTI-01 \
     I-SLTIU-01 \
     I-BEQ-01 \
@@ -80,10 +77,16 @@ rv32i_sc_tests = \
     I-CSRRSI-01 \
     I-CSRRC-01 \
     I-CSRRCI-01 \
-    I-ECALL-01 \
-    I-EBREAK-01 \
     I-IO \
 
+    # These tests are currently removed since the underlying core in opentitan
+    # does not yet support FENCE.I instructions
+    #I-MISALIGN_JMP-01
+    #I-MISALIGN_LDST-01
+    #I-FENCE.I-01
+    #I-ECALL-01
+    #I-EBREAK-01
+
 
 rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
 
-- 
2.24.0.rc1.363.gb1bccd3e3d-goog