[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 93ca392..e560690 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -3674,7 +3674,7 @@
rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40150000
- generated: "true"
+ attr: templated
localparam:
{
EscCntDw: 32
@@ -3863,7 +3863,7 @@
}
domain: Aon
base_addr: 0x40400000
- generated: "true"
+ attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
@@ -4103,7 +4103,7 @@
}
domain: Aon
base_addr: 0x40410000
- generated: "true"
+ attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
@@ -4236,7 +4236,7 @@
}
domain: Aon
base_addr: 0x40420000
- generated: "true"
+ attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
@@ -4428,7 +4428,7 @@
}
domain: Aon
base_addr: 0x40460000
- generated: "true"
+ attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
@@ -4665,7 +4665,7 @@
}
domain: Aon
base_addr: 0x40470000
- generated: "true"
+ attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_timers
@@ -4771,6 +4771,55 @@
]
}
{
+ name: ast
+ type: ast
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ clock_group: secure
+ clock_reset_export:
+ [
+ ast
+ ]
+ reset_connections:
+ {
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x40480000
+ attr: reggen_only
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_secure
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list: []
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: ast
+ index: -1
+ }
+ ]
+ }
+ {
name: sensor_ctrl_aon
type: sensor_ctrl
clock_srcs:
@@ -4788,7 +4837,7 @@
}
domain: Aon
base_addr: 0x40490000
- top_only: "true"
+ attr: reggen_top
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
@@ -5135,7 +5184,7 @@
rst_otp_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41000000
- generated: "true"
+ attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
@@ -5516,7 +5565,7 @@
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41010000
- generated: "true"
+ attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
@@ -8082,7 +8131,7 @@
sensor_ctrl_aon.ast_status: sensor_ctrl_ast_status
usbdev.usb_ref_val: ""
usbdev.usb_ref_pulse: ""
- peri.tl_ast_wrapper: ast_tl
+ peri.tl_ast: ast_tl
otp_ctrl.otp_ast_pwr_seq: ""
otp_ctrl.otp_ast_pwr_seq_h: ""
eflash.flash_bist_enable: flash_bist_enable
@@ -8800,7 +8849,7 @@
lc_ctrl
sensor_ctrl_aon
alert_handler
- ast_wrapper
+ ast
sram_ctrl_ret_aon
aon_timer_aon
]
@@ -9269,12 +9318,12 @@
pipeline_byp: "true"
}
{
- name: ast_wrapper
+ name: ast
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
- stub: true
+ inst_type: ast
addr_range:
[
{
@@ -9283,6 +9332,7 @@
}
]
xbar: false
+ stub: true
pipeline_byp: "true"
}
]
@@ -9605,7 +9655,7 @@
{
struct: tl
type: req_rsp
- name: tl_ast_wrapper
+ name: tl_ast
act: req
package: tlul_pkg
inst_name: peri
@@ -12364,6 +12414,10 @@
aon_peri
usb_peri
]
+ ast:
+ [
+ io_div4_secure
+ ]
sensor_ctrl_aon:
[
io_div4_secure
@@ -12413,6 +12467,10 @@
sys_aon
usb
]
+ ast:
+ [
+ sys_io_div4
+ ]
sensor_ctrl_aon:
[
sys_io_div4
@@ -14068,6 +14126,15 @@
index: -1
}
{
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: ast
+ index: -1
+ }
+ {
struct: ast_alert
type: req_rsp
name: ast_alert
@@ -15708,7 +15775,7 @@
{
struct: tl
type: req_rsp
- name: tl_ast_wrapper
+ name: tl_ast
act: req
package: tlul_pkg
inst_name: peri
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
index 45edc43..3341f24 100644
--- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -74,7 +74,7 @@
tl_if alert_handler_tl_if(clk_io_div4, rst_n);
tl_if sram_ctrl_ret_aon_tl_if(clk_io_div4, rst_n);
tl_if aon_timer_aon_tl_if(clk_io_div4, rst_n);
-tl_if ast_wrapper_tl_if(clk_io_div4, rst_n);
+tl_if ast_tl_if(clk_io_div4, rst_n);
initial begin
bit xbar_mode;
@@ -144,7 +144,7 @@
`DRIVE_CHIP_TL_DEVICE_IF(alert_handler, alert_handler, tl)
`DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_ret_aon, sram_ctrl_ret_aon, tl)
`DRIVE_CHIP_TL_DEVICE_IF(aon_timer_aon, aon_timer_aon, tl)
- `DRIVE_CHIP_TL_EXT_DEVICE_IF(ast_wrapper, ast_tl)
+ `DRIVE_CHIP_TL_EXT_DEVICE_IF(ast, ast_tl)
end
end
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
index c341aee..ab6a0be 100644
--- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -130,7 +130,7 @@
'{"aon_timer_aon", '{
'{32'h40470000, 32'h40470fff}
}},
- '{"ast_wrapper", '{
+ '{"ast", '{
'{32'h40480000, 32'h40480fff}
}}};
@@ -170,7 +170,7 @@
"lc_ctrl",
"sensor_ctrl_aon",
"alert_handler",
- "ast_wrapper",
+ "ast",
"sram_ctrl_ret_aon",
"aon_timer_aon",
"flash_ctrl",
@@ -213,7 +213,7 @@
"lc_ctrl",
"sensor_ctrl_aon",
"alert_handler",
- "ast_wrapper",
+ "ast",
"sram_ctrl_ret_aon",
"aon_timer_aon",
"flash_ctrl",
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_reg_pkg.sv b/hw/top_earlgrey/ip/ast/rtl/ast_reg_pkg.sv
index 8c68bad..ce1b3cd 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_reg_pkg.sv
@@ -6,14 +6,13 @@
package ast_reg_pkg;
+ // Address width within the block
+ parameter int BlockAw = 3;
+
////////////////////////////
// Typedefs for registers //
////////////////////////////
typedef struct packed {
- logic [7:0] q;
- } ast_reg2hw_revid_reg_t;
-
- typedef struct packed {
logic [31:0] q;
} ast_reg2hw_rwtype0_reg_t;
@@ -43,7 +42,6 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- ast_reg2hw_revid_reg_t revid; // [50:43]
ast_reg2hw_rwtype0_reg_t rwtype0; // [42:11]
ast_reg2hw_rwtype1_reg_t rwtype1; // [10:0]
} ast_reg2hw_t;
@@ -56,23 +54,19 @@
} ast_hw2reg_t;
// Register Address
- parameter logic [3:0] AST_REVID_OFFSET = 4'h 0;
- parameter logic [3:0] AST_RWTYPE0_OFFSET = 4'h 4;
- parameter logic [3:0] AST_RWTYPE1_OFFSET = 4'h 8;
-
+ parameter logic [BlockAw-1:0] AST_RWTYPE0_OFFSET = 3'h 0;
+ parameter logic [BlockAw-1:0] AST_RWTYPE1_OFFSET = 3'h 4;
// Register Index
typedef enum int {
- AST_REVID,
AST_RWTYPE0,
AST_RWTYPE1
} ast_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] AST_PERMIT [3] = '{
- 4'b 0001, // index[0] AST_REVID
- 4'b 1111, // index[1] AST_RWTYPE0
- 4'b 0011 // index[2] AST_RWTYPE1
+ parameter logic [3:0] AST_PERMIT [2] = '{
+ 4'b 1111, // index[0] AST_RWTYPE0
+ 4'b 0011 // index[1] AST_RWTYPE1
};
endpackage
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv b/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
index 0595b08..379330d 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
@@ -23,7 +23,7 @@
import ast_reg_pkg::* ;
- localparam int AW = 4;
+ localparam int AW = 3;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
@@ -43,8 +43,22 @@
tlul_pkg::tl_h2d_t tl_reg_h2d;
tlul_pkg::tl_d2h_t tl_reg_d2h;
+ // incoming payload check
+ logic chk_err;
+ tlul_payload_chk u_chk (
+ .tl_i,
+ .err_o(chk_err)
+ );
+
+ // outgoing payload generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_gen_payload_chk u_gen_chk (
+ .tl_i(tl_o_pre),
+ .tl_o
+ );
+
assign tl_reg_h2d = tl_i;
- assign tl_o = tl_reg_d2h;
+ assign tl_o_pre = tl_reg_d2h;
tlul_adapter_reg #(
.RegAw(AW),
@@ -66,12 +80,11 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
- logic [7:0] revid_qs;
logic [31:0] rwtype0_qs;
logic [31:0] rwtype0_wd;
logic rwtype0_we;
@@ -89,32 +102,6 @@
logic rwtype1_field15_8_we;
// Register instances
- // R[revid]: V(False)
-
- prim_subreg #(
- .DW (8),
- .SWACCESS("RO"),
- .RESVAL (8'h1)
- ) u_revid (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- .we (1'b0),
- .wd ('0 ),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.revid.q ),
-
- // to register interface (read)
- .qs (revid_qs)
- );
-
-
// R[rwtype0]: V(False)
prim_subreg #(
@@ -250,12 +237,11 @@
- logic [2:0] addr_hit;
+ logic [1:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[0] = (reg_addr == AST_REVID_OFFSET);
- addr_hit[1] = (reg_addr == AST_RWTYPE0_OFFSET);
- addr_hit[2] = (reg_addr == AST_RWTYPE1_OFFSET);
+ addr_hit[0] = (reg_addr == AST_RWTYPE0_OFFSET);
+ addr_hit[1] = (reg_addr == AST_RWTYPE1_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -265,23 +251,21 @@
wr_err = 1'b0;
if (addr_hit[0] && reg_we && (AST_PERMIT[0] != (AST_PERMIT[0] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[1] && reg_we && (AST_PERMIT[1] != (AST_PERMIT[1] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[2] && reg_we && (AST_PERMIT[2] != (AST_PERMIT[2] & reg_be))) wr_err = 1'b1 ;
end
-
- assign rwtype0_we = addr_hit[1] & reg_we & ~wr_err;
+ assign rwtype0_we = addr_hit[0] & reg_we & ~wr_err;
assign rwtype0_wd = reg_wdata[31:0];
- assign rwtype1_field0_we = addr_hit[2] & reg_we & ~wr_err;
+ assign rwtype1_field0_we = addr_hit[1] & reg_we & ~wr_err;
assign rwtype1_field0_wd = reg_wdata[0];
- assign rwtype1_field1_we = addr_hit[2] & reg_we & ~wr_err;
+ assign rwtype1_field1_we = addr_hit[1] & reg_we & ~wr_err;
assign rwtype1_field1_wd = reg_wdata[1];
- assign rwtype1_field4_we = addr_hit[2] & reg_we & ~wr_err;
+ assign rwtype1_field4_we = addr_hit[1] & reg_we & ~wr_err;
assign rwtype1_field4_wd = reg_wdata[4];
- assign rwtype1_field15_8_we = addr_hit[2] & reg_we & ~wr_err;
+ assign rwtype1_field15_8_we = addr_hit[1] & reg_we & ~wr_err;
assign rwtype1_field15_8_wd = reg_wdata[15:8];
// Read data return
@@ -289,14 +273,10 @@
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
- reg_rdata_next[7:0] = revid_qs;
- end
-
- addr_hit[1]: begin
reg_rdata_next[31:0] = rwtype0_qs;
end
- addr_hit[2]: begin
+ addr_hit[1]: begin
reg_rdata_next[0] = rwtype1_field0_qs;
reg_rdata_next[1] = rwtype1_field1_qs;
reg_rdata_next[4] = rwtype1_field4_qs;
@@ -309,6 +289,15 @@
endcase
end
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
// Assertions for Register Interface
`ASSERT_PULSE(wePulse, reg_we)
`ASSERT_PULSE(rePulse, reg_re)
@@ -319,10 +308,6 @@
// this is formulated as an assumption such that the FPV testbenches do disprove this
// property by mistake
- // this is formulated as an assumption such that the FPV testbenches do disprove this
- // property by mistake
- // TODO may need to change this soon
- `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
-
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
endmodule
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
index 8821642..540e888 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -629,6 +629,7 @@
assign clocks_ast_o.clk_ast_usbdev_io_div4_peri = clocks_o.clk_io_div4_peri;
assign clocks_ast_o.clk_ast_usbdev_aon_peri = clocks_o.clk_aon_peri;
assign clocks_ast_o.clk_ast_usbdev_usb_peri = clocks_o.clk_usb_peri;
+ assign clocks_ast_o.clk_ast_ast_io_div4_secure = clocks_o.clk_io_div4_secure;
assign clocks_ast_o.clk_ast_sensor_ctrl_aon_io_div4_secure = clocks_o.clk_io_div4_secure;
assign clocks_ast_o.clk_ast_entropy_src_main_secure = clocks_o.clk_main_secure;
assign clocks_ast_o.clk_ast_edn0_main_secure = clocks_o.clk_main_secure;
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
index 3c36aaf..6484d72 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
@@ -49,6 +49,7 @@
logic clk_ast_usbdev_io_div4_peri;
logic clk_ast_usbdev_aon_peri;
logic clk_ast_usbdev_usb_peri;
+ logic clk_ast_ast_io_div4_secure;
logic clk_ast_sensor_ctrl_aon_io_div4_secure;
logic clk_ast_entropy_src_main_secure;
logic clk_ast_edn0_main_secure;
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
index 59f2eef..6b0771b 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -747,6 +747,7 @@
assign resets_ast_o.rst_ast_usbdev_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
assign resets_ast_o.rst_ast_usbdev_sys_aon_n = resets_o.rst_sys_aon_n;
assign resets_ast_o.rst_ast_usbdev_usb_n = resets_o.rst_usb_n;
+ assign resets_ast_o.rst_ast_ast_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
assign resets_ast_o.rst_ast_sensor_ctrl_aon_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
assign resets_ast_o.rst_ast_entropy_src_sys_n = resets_o.rst_sys_n;
assign resets_ast_o.rst_ast_edn0_sys_n = resets_o.rst_sys_n;
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
index 2ec70e9..c391444 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
@@ -65,6 +65,7 @@
logic [PowerDomains-1:0] rst_ast_usbdev_sys_io_div4_n;
logic [PowerDomains-1:0] rst_ast_usbdev_sys_aon_n;
logic [PowerDomains-1:0] rst_ast_usbdev_usb_n;
+ logic [PowerDomains-1:0] rst_ast_ast_sys_io_div4_n;
logic [PowerDomains-1:0] rst_ast_sensor_ctrl_aon_sys_io_div4_n;
logic [PowerDomains-1:0] rst_ast_entropy_src_sys_n;
logic [PowerDomains-1:0] rst_ast_edn0_sys_n;
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index 705cb2d..2d639e8 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -50,7 +50,7 @@
lc_ctrl
sensor_ctrl_aon
alert_handler
- ast_wrapper
+ ast
sram_ctrl_ret_aon
aon_timer_aon
]
@@ -519,12 +519,12 @@
pipeline_byp: "true"
}
{
- name: ast_wrapper
+ name: ast
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
- stub: true
+ inst_type: ast
addr_range:
[
{
@@ -533,6 +533,7 @@
}
]
xbar: false
+ stub: true
pipeline_byp: "true"
}
]
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
index 6f34e7c..40d507b 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
@@ -171,7 +171,7 @@
}
{ struct: "tl"
type: "req_rsp"
- name: "tl_ast_wrapper"
+ name: "tl_ast"
act: "req"
package: "tlul_pkg"
}
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
index b1b99f0..d7e2b63 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
@@ -42,4 +42,4 @@
`CONNECT_TL_DEVICE_IF(alert_handler, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(sram_ctrl_ret_aon, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(aon_timer_aon, dut, clk_peri_i, rst_n)
-`CONNECT_TL_DEVICE_IF(ast_wrapper, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(ast, dut, clk_peri_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
index c2328af..838f7aa 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
@@ -105,10 +105,10 @@
-node tb.dut tl_aon_timer_aon_o.a_address[21:19]
-node tb.dut tl_aon_timer_aon_o.a_address[29:23]
-node tb.dut tl_aon_timer_aon_o.a_address[31:31]
--node tb.dut tl_ast_wrapper_o.a_address[18:12]
--node tb.dut tl_ast_wrapper_o.a_address[21:20]
--node tb.dut tl_ast_wrapper_o.a_address[29:23]
--node tb.dut tl_ast_wrapper_o.a_address[31:31]
+-node tb.dut tl_ast_o.a_address[18:12]
+-node tb.dut tl_ast_o.a_address[21:20]
+-node tb.dut tl_ast_o.a_address[29:23]
+-node tb.dut tl_ast_o.a_address[31:31]
begin tgl
-tree tb
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
index f47b388..6f79c7a 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -82,7 +82,7 @@
'{"aon_timer_aon", '{
'{32'h40470000, 32'h40470fff}
}},
- '{"ast_wrapper", '{
+ '{"ast", '{
'{32'h40480000, 32'h40480fff}
}}};
@@ -112,7 +112,7 @@
"lc_ctrl",
"sensor_ctrl_aon",
"alert_handler",
- "ast_wrapper",
+ "ast",
"sram_ctrl_ret_aon",
"aon_timer_aon"}}
};
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
index e06bd14..8c51fc6 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -164,11 +164,11 @@
.h2d (tl_aon_timer_aon_o),
.d2h (tl_aon_timer_aon_i)
);
- bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_ast_wrapper (
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_ast (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .h2d (tl_ast_wrapper_o),
- .d2h (tl_ast_wrapper_i)
+ .h2d (tl_ast_o),
+ .d2h (tl_ast_i)
);
endmodule
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
index 5676e89..93e338d 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -31,7 +31,7 @@
localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 40150000;
localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET_AON = 32'h 40500000;
localparam logic [31:0] ADDR_SPACE_AON_TIMER_AON = 32'h 40470000;
- localparam logic [31:0] ADDR_SPACE_AST_WRAPPER = 32'h 40480000;
+ localparam logic [31:0] ADDR_SPACE_AST = 32'h 40480000;
localparam logic [31:0] ADDR_MASK_UART0 = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_UART1 = 32'h 00000fff;
@@ -58,7 +58,7 @@
localparam logic [31:0] ADDR_MASK_ALERT_HANDLER = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET_AON = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_AON_TIMER_AON = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_AST_WRAPPER = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_AST = 32'h 00000fff;
localparam int N_HOST = 1;
localparam int N_DEVICE = 26;
@@ -89,7 +89,7 @@
TlAlertHandler = 22,
TlSramCtrlRetAon = 23,
TlAonTimerAon = 24,
- TlAstWrapper = 25
+ TlAst = 25
} tl_device_e;
typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
index cd28ac6..d31b63b 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -31,7 +31,7 @@
// -> lc_ctrl
// -> sensor_ctrl_aon
// -> alert_handler
-// -> ast_wrapper
+// -> ast
// -> sram_ctrl_ret_aon
// -> aon_timer_aon
@@ -94,8 +94,8 @@
input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_aon_i,
output tlul_pkg::tl_h2d_t tl_aon_timer_aon_o,
input tlul_pkg::tl_d2h_t tl_aon_timer_aon_i,
- output tlul_pkg::tl_h2d_t tl_ast_wrapper_o,
- input tlul_pkg::tl_d2h_t tl_ast_wrapper_i,
+ output tlul_pkg::tl_h2d_t tl_ast_o,
+ input tlul_pkg::tl_d2h_t tl_ast_i,
input lc_ctrl_pkg::lc_tx_t scanmode_i
);
@@ -189,8 +189,8 @@
assign tl_alert_handler_o = tl_s1n_27_ds_h2d[22];
assign tl_s1n_27_ds_d2h[22] = tl_alert_handler_i;
- assign tl_ast_wrapper_o = tl_s1n_27_ds_h2d[23];
- assign tl_s1n_27_ds_d2h[23] = tl_ast_wrapper_i;
+ assign tl_ast_o = tl_s1n_27_ds_h2d[23];
+ assign tl_s1n_27_ds_d2h[23] = tl_ast_i;
assign tl_sram_ctrl_ret_aon_o = tl_s1n_27_ds_h2d[24];
assign tl_s1n_27_ds_d2h[24] = tl_sram_ctrl_ret_aon_i;
@@ -273,7 +273,7 @@
end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
dev_sel_s1n_27 = 5'd22;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin
+ end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_AST)) == ADDR_SPACE_AST) begin
dev_sel_s1n_27 = 5'd23;
end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET_AON)) == ADDR_SPACE_SRAM_CTRL_RET_AON) begin
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 20f916b..e80df10 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -2422,9 +2422,9 @@
.tl_aon_timer_aon_o(aon_timer_aon_tl_req),
.tl_aon_timer_aon_i(aon_timer_aon_tl_rsp),
- // port: tl_ast_wrapper
- .tl_ast_wrapper_o(ast_tl_req_o),
- .tl_ast_wrapper_i(ast_tl_rsp_i),
+ // port: tl_ast
+ .tl_ast_o(ast_tl_req_o),
+ .tl_ast_i(ast_tl_rsp_i),
.scanmode_i
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index f67dc42..11eb9e5 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -232,6 +232,16 @@
parameter int unsigned TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES = 32'h1000;
/**
+ * Peripheral base address for ast in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_AST_BASE_ADDR = 32'h40480000;
+
+ /**
+ * Peripheral size in bytes for ast in top earlgrey.
+ */
+ parameter int unsigned TOP_EARLGREY_AST_SIZE_BYTES = 32'h1000;
+
+ /**
* Peripheral base address for sensor_ctrl_aon in top earlgrey.
*/
parameter int unsigned TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR = 32'h40490000;
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index d9b0c8a..04addb6 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -422,6 +422,24 @@
#define TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES 0x1000u
/**
+ * Peripheral base address for ast in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_AST_BASE_ADDR 0x40480000u
+
+/**
+ * Peripheral size for ast in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_AST_BASE_ADDR and
+ * `TOP_EARLGREY_AST_BASE_ADDR + TOP_EARLGREY_AST_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_AST_SIZE_BYTES 0x1000u
+
+/**
* Peripheral base address for sensor_ctrl_aon in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
