Updates for ROM - Allow FPGA to use real ROM - Allow reset to be used in prim_rom - Qualify tlul_adapter_sram response to block d_valid if there are no pending requests

diff --git a/hw/ip/prim/abstract/prim_rom.sv b/hw/ip/prim/abstract/prim_rom.sv
index 1bd8439..b0adecc 100644
--- a/hw/ip/prim/abstract/prim_rom.sv
+++ b/hw/ip/prim/abstract/prim_rom.sv

@@ -9,6 +9,7 @@
   parameter  int Aw        = $clog2(Depth)
 ) (
   input                        clk_i,
+  input                        rst_ni,
   input        [Aw-1:0]        addr_i,
   input                        cs_i,
   output logic [Width-1:0]     dout_o,
@@ -21,6 +22,7 @@
       .Depth(Depth)
     ) u_impl_generic (
       .clk_i,
+      .rst_ni,
       .addr_i,
       .cs_i,
       .dout_o,

diff --git a/hw/ip/prim_generic/rtl/prim_generic_rom.sv b/hw/ip/prim_generic/rtl/prim_generic_rom.sv
index c400c67..398a9fb 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_rom.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_rom.sv

@@ -8,6 +8,7 @@
   parameter  int Aw        = $clog2(Depth)
 ) (
   input                        clk_i,
+  input                        rst_ni,
   input        [Aw-1:0]        addr_i,
   input                        cs_i,
   output logic [Width-1:0]     dout_o,
@@ -22,8 +23,12 @@
     end
   end
 
-  always_ff @(posedge clk_i) begin
-    dvalid_o <= cs_i;
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      dvalid_o <= 1'b0;
+    end else begin
+      dvalid_o <= cs_i;
+    end
   end
 
   // ******************************************************************************

diff --git a/hw/ip/tlul/rtl/tlul_adapter_sram.sv b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
index 3004a05..fac39c4 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_sram.sv
+++ b/hw/ip/tlul/rtl/tlul_adapter_sram.sv

@@ -125,7 +125,7 @@
   }; // Store the request only. Doesn't have to store data
   assign reqfifo_rready = tl_o.d_valid & tl_i.d_ready ;
 
-  assign rspfifo_wvalid = rvalid_i ;
+  assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid;
   assign rspfifo_wdata  = '{
     data:  rdata_i,
     error: rerror_i[1]  // Only care for Uncorrectable error

diff --git a/hw/top_earlgrey/doc/top_earlgrey.tpl.sv b/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
index 3d78507..92d564e 100644
--- a/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
+++ b/hw/top_earlgrey/doc/top_earlgrey.tpl.sv

@@ -274,6 +274,7 @@
     .Depth(${rom_depth})
   ) u_rom_${m["name"]} (
     .clk_i,
+    .rst_ni   (ndmreset_n),
     .cs_i     (${m["name"]}_req),
     .addr_i   (${m["name"]}_addr),
     .dout_o   (${m["name"]}_rdata),

diff --git a/hw/top_earlgrey/rtl/top_earlgrey.sv b/hw/top_earlgrey/rtl/top_earlgrey.sv
index 0e5733f..4a6fad9 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey.sv

@@ -219,6 +219,7 @@
     .Depth(2048)
   ) u_rom_rom (
     .clk_i,
+    .rst_ni   (ndmreset_n),
     .cs_i     (rom_req),
     .addr_i   (rom_addr),
     .dout_o   (rom_rdata),

diff --git a/hw/top_earlgrey/top_earlgrey_nexysvideo.core b/hw/top_earlgrey/top_earlgrey_nexysvideo.core
index ecd16ba..334ca5d 100644
--- a/hw/top_earlgrey/top_earlgrey_nexysvideo.core
+++ b/hw/top_earlgrey/top_earlgrey_nexysvideo.core

@@ -26,11 +26,6 @@
   # XXX: The VMEM file should be added to the sources of the Vivado project to
   # make the Vivado dependency tracking work. However this requires changes to
   # fusesoc first.
-  SRAM_INIT_FILE:
-    datatype: str
-    description: SRAM initialization file in vmem hex format
-    default: "../../../../../sw/boot_rom/boot_rom.vmem"
-    paramtype: vlogdefine
   ROM_INIT_FILE:
     datatype: str
     description: SRAM initialization file in vmem hex format
@@ -49,10 +44,7 @@
       - files_constraints
     toplevel: top_earlgrey_nexysvideo
     parameters:
-      - SRAM_INIT_FILE
-      # To initialize the ROM, uncomment below and set ROM_INIT_FILE to a
-      # path of a VMEM file containing the ROM code.
-      #- ROM_INIT_FILE
+      - ROM_INIT_FILE
       - PRIM_DEFAULT_IMPL=xilinx
     tools:
       vivado: