| commit | b0f2f65dc29fc771d74c331d5ae5fedb0e2db77f | [log] [tgz] |
|---|---|---|
| author | Srikrishna Iyer <sriyer@google.com> | Tue Aug 02 01:30:56 2022 -0700 |
| committer | Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> | Wed Aug 03 18:54:36 2022 -0700 |
| tree | fb772adb10ec9cfd708447a01fadee9b8adcb04e | |
| parent | ba6eea9b5c9fa4fe9a1ad980a7f31348affde14c [diff] |
[rv_dm, dv] Fixes for sberror=2,7 support Previously, if the SBA TL access returned an error response, it would have not impact (i.e. it would not show up) in the DMI SBCS status register, and the debugger would have no way of knowing an erroneous response occurred. Likewise, if the SBA TL response had a data integrity error, it would also not show up. The recent changes to the PULP debug module added support for indicating device error response as sberror=2 and also allowed TL device intg error to be indicated as other error (sberror=7). This commit updates the sba_access_utils_pkg (monitor and the utility tasks) and the RV_DM testbench (sequences and the scoreboard with fixes needed to support this design change. The sba access monitor can only predict sberror=3,4. It now wires the actual sberror value seen when polling the sbcs for status into the predicted SBA access item that is written to the analysis port. The rv_dm scoreboard which retrieves the item checks the correctness of sberror=2,7 based on the monitored TL transaction. The sba access util tasks have minor flow related enhancements to ensure the accesses to SBA registers in the DMI space are sequenced corrected to properly facilitate a SBA TL access. The rv_dm sba test sequences have similar fixes to properly sequence events to avoid unexpected bahaviors. The injection of SBA TL device error response and SBA TL device intg error is now disbled in the base sequence class, which now does only does clean accesses. These are constrained-randomized in the extended vseq classes instead, since they have a real impact on the behavior of the PULP debug module's SBA logic. Signed-off-by: Srikrishna Iyer <sriyer@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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