[edn/dv] dv doc, testplan, checklist, regression, csrng_agent mod, whitespace removed
Signed-off-by: Steve Nelson <steve.nelson@wdc.com>
diff --git a/hw/ip/csrng/doc/checklist.md b/hw/ip/csrng/doc/checklist.md
index 91d87b7..b6395a4 100755
--- a/hw/ip/csrng/doc/checklist.md
+++ b/hw/ip/csrng/doc/checklist.md
@@ -52,7 +52,7 @@
RTL | [REVIEW_TODO][] | Pending |
RTL | [STYLE_X][] | Done |
Code Quality | [LINT_PASS][] | Done |
-Code Quality | [CDC_SETUP][] | Waived | CDC flow is not available yet.
+Code Quality | [CDC_SETUP][] | Waived | CDC flow is not available yet.
Code Quality | [FPGA_TIMING][] | Done |
Code Quality | [CDC_SYNCMACRO][] | Waived |
Security | [SEC_CM_IMPLEMENTED][] | Not Started |
diff --git a/hw/ip/edn/data/edn_testplan.hjson b/hw/ip/edn/data/edn_testplan.hjson
index 2b4103e..81823f0 100644
--- a/hw/ip/edn/data/edn_testplan.hjson
+++ b/hw/ip/edn/data/edn_testplan.hjson
@@ -13,7 +13,7 @@
name: smoke
desc: '''
Enable edn, let edn boot mode generate csrng instantiate/generate commands,
- endpoint requests genbits, compare csrng/endpoint genbits.
+ endpoint requests genbits, compare csrng/endpoint genbits.
'''
milestone: V1
tests: ["edn_smoke"]
@@ -21,11 +21,12 @@
{
name: firmware
desc: '''
- Verify regwen bit enables/disables write access to control registers
+ Verify regwen bit enables/disables write access to control registers.
Verify SW_CMD_REQ/SW_CMD_STS registers/bits behave as predicted.
+ Verify RESEED/GENERATE software cmds work with/without additional data.
Verify cmd_fifo_reset bit causes fifos to reset.
- Verify boot_req_dis bit disables boot_req mode
- Verify registers at End-Of-Test
+ Verify boot_req_dis bit disables boot_req mode.
+ Verify registers at End-Of-Test.
'''
milestone: V2
tests: []
@@ -37,7 +38,7 @@
Verify auto-request mode (RESEED_CMD/GENERATE_CMD registers) behaves as predicted.
Verify max_num_reqs_between_reseeds in auto-generate mode.
Verify boot-time request mode behaves as predicted.
- Verify SUM_STS register bits behave as predicted.
+ Verify SUM_STS register bits behave as predicted.
'''
milestone: V2
tests: []
@@ -56,7 +57,7 @@
desc: '''
Verify intr_edn_cmd_req_done interrupt asserts/clears as predicted.
Verify intr_edn_fatal_err interrupt asserts/clears as predicted.
- Verify ERR_CODE all reg bits via ERR_CODE_TEST.
+ Verify ERR_CODE all reg bits via ERR_CODE_TEST.
'''
milestone: V2
tests: []
diff --git a/hw/ip/edn/doc/dv/index.md b/hw/ip/edn/doc/dv/index.md
index 701e55a..2ff5d1c 100644
--- a/hw/ip/edn/doc/dv/index.md
+++ b/hw/ip/edn/doc/dv/index.md
@@ -32,8 +32,6 @@
* Interrupts ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}})
* Alerts ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}})
* Devmode ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}})
-* Csrng ([`csrng_if`]({{< relref "hw/dv/sv/csrng_agent" >}})
-* Endpoints ([`push_pull_if`]({{< relref "hw/dv/sv/push_pull_agent" >}})
### Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
diff --git a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv
index 063283e..66aa3c5 100644
--- a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv
+++ b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv
@@ -27,7 +27,7 @@
// setup basic entropy_src features
virtual task entropy_src_init();
-
+
cfg.efuse_es_sw_reg_en_vif.drive_pin(.idx(0), .val(cfg.efuse_es_sw_reg_en));
endtask
diff --git a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_rng_vseq.sv b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_rng_vseq.sv
index c38a407..89305c8 100644
--- a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_rng_vseq.sv
+++ b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_rng_vseq.sv
@@ -11,12 +11,12 @@
task body();
// TODO: Temporary for developing rng_agent
// Enable/Disable rng
- csr_wr(.csr(ral.conf), .value(5'h10));
- csr_wr(.csr(ral.conf), .value(5'h00));
- csr_wr(.csr(ral.conf), .value(5'h10));
- csr_wr(.csr(ral.conf), .value(5'h00));
- csr_wr(.csr(ral.conf), .value(5'h10));
- csr_wr(.csr(ral.conf), .value(5'h00));
+ csr_wr(.csr(ral.conf), .value(5'h10));
+ csr_wr(.csr(ral.conf), .value(5'h00));
+ csr_wr(.csr(ral.conf), .value(5'h10));
+ csr_wr(.csr(ral.conf), .value(5'h00));
+ csr_wr(.csr(ral.conf), .value(5'h10));
+ csr_wr(.csr(ral.conf), .value(5'h00));
endtask : body
endclass : entropy_src_rng_vseq
diff --git a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_smoke_vseq.sv b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_smoke_vseq.sv
index 8c93b0a..c69b25a 100644
--- a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_smoke_vseq.sv
+++ b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_smoke_vseq.sv
@@ -36,7 +36,7 @@
// Ensure entropy_valid interrupt bit cleared
csr_rd_check(.ptr(ral.intr_state), .compare_value(1'b0));
-
+
endtask : body
endclass : entropy_src_smoke_vseq
diff --git a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
index 2dbe98e..3d3201f 100644
--- a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
+++ b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
@@ -18,6 +18,7 @@
"{proj_root}/hw/ip/aon_timer/dv/aon_timer_sim_cfg.hjson",
"{proj_root}/hw/ip/csrng/dv/csrng_sim_cfg.hjson",
"{proj_root}/hw/ip/dcd/dv/dcd_sim_cfg.hjson",
+ "{proj_root}/hw/ip/edn/dv/edn_sim_cfg.hjson",
"{proj_root}/hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson",
"{proj_root}/hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson",
"{proj_root}/hw/ip/gpio/dv/gpio_sim_cfg.hjson",
