| commit | 456e53d6f541a3fd3dcc1cdc310c9c5bf8f789b4 | [log] [tgz] |
|---|---|---|
| author | Cindy Chen <chencindy@google.com> | Wed Sep 30 17:04:09 2020 -0700 |
| committer | cindychip <cindy.chen0316@gmail.com> | Wed Sep 30 19:54:08 2020 -0700 |
| tree | 1a3b87161a0bb26e9e61cfc354723243a2ac2d2a | |
| parent | 306de93b6c29546156e4433d4a7e7acb8780630e [diff] |
[dv] fix top-level csr failure Fix Top-level csr automation test failures due to: 1. pwrmgr register wake_status cannot be automatically predicted in csr test. So excluded from csr read check 2. Top level shadow_reg has async alert_sender clocks. Previously to make alert storage error, I waited for one clock cycle then backdoor write back to original value. This will ensure only one alert is triggered. But in top-level async mode, one clock cycle for main_clock might be less than one cycle alert_sender clock. Which will cause the storage_error to be ignored. Signed-off-by: Cindy Chen <chencindy@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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