[reggen] Always connect read enable signal to shadow regs
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/util/reggen/reg_top.sv.tpl b/util/reggen/reg_top.sv.tpl
index 07cc541..3f19505 100644
--- a/util/reggen/reg_top.sv.tpl
+++ b/util/reggen/reg_top.sv.tpl
@@ -663,7 +663,7 @@
reg_name = reg.name.lower()
clk_expr = reg.async_clk.clock if reg.async_clk else reg_clk_expr
rst_expr = reg.async_clk.reset if reg.async_clk else reg_rst_expr
- re_expr = f'{reg_name}_re' if field.swaccess.allows_read() else "1'b0"
+ re_expr = f'{reg_name}_re' if field.swaccess.allows_read() or reg.shadowed else "1'b0"
# software inputs to field instance, write enable, read enable, write data
if field.swaccess.allows_write():
diff --git a/util/reggen/register.py b/util/reggen/register.py
index ffdc01a..2d4f1d3 100644
--- a/util/reggen/register.py
+++ b/util/reggen/register.py
@@ -341,8 +341,12 @@
This is true if any of the following are true:
- - The register is shadowed (because shadow registers need to know
- about reads)
+ - The register is shadowed, because the read has a side effect.
+ I.e., this puts the register back into Phase 0 (next write will
+ go to the staged register). This is useful for software in case
+ it lost track of the current phase. See comportability spec for
+ more details:
+ https://docs.opentitan.org/doc/rm/register_tool/#shadow-registers
- There's an RC field (where we'll attach the read-enable signal to
the subreg's we port)
