[flash_ctrl/dv] Ordering data types and some CS model related updates
Signed-off-by: Eitan Shapira <eitanshapira89@gmail.com>
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
index ccb9b14..e6c6554 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
@@ -37,10 +37,10 @@
bit bank_erase_enable = 1;
// mem for scoreboard
- data_t scb_flash_data[addr_t] = '{default: 1};
- data_t scb_flash_info[addr_t] = '{default: 1};
- data_t scb_flash_info1[addr_t] = '{default: 1};
- data_t scb_flash_info2[addr_t] = '{default: 1};
+ data_model_t scb_flash_data = '{default: 1};
+ data_model_t scb_flash_info = '{default: 1};
+ data_model_t scb_flash_info1 = '{default: 1};
+ data_model_t scb_flash_info2 = '{default: 1};
// Max delay for alerts in clocks
uint alert_max_delay;
@@ -56,7 +56,7 @@
string flash_ral_name = "flash_ctrl_eflash_reg_block";
- virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+ virtual function void initialize(addr_t csr_base_addr = '1);
list_of_alerts = flash_ctrl_env_pkg::LIST_OF_ALERTS;
has_shadowed_regs = 1;
tl_intg_alert_name = "fatal_std_err";
@@ -89,6 +89,17 @@
`uvm_info(`gfn, $sformatf("ral_model_names: %0p", ral_model_names), UVM_LOW)
endfunction : initialize
+ // For a given partition returns its size in bytes in each of the banks.
+ function uint get_partition_words_num(flash_dv_part_e part);
+ case(part)
+ FlashPartData: return BytesPerBank / 4;
+ FlashPartInfo: return InfoTypeBytes[0] / 4;
+ FlashPartInfo1: return InfoTypeBytes[1] / 4;
+ FlashPartInfo2: return InfoTypeBytes[2] / 4;
+ default: `uvm_error(`gfn, $sformatf("Undefined partition - %s", part.name()))
+ endcase
+ endfunction : get_partition_words_num
+
// Backdoor initialize flash memory elements.
//
// Applies the initialization scheme to the given flash partition in all banks.
@@ -109,6 +120,9 @@
FlashMemInitInvalidate: begin
foreach (mem_bkdr_util_h[part][i]) mem_bkdr_util_h[part][i].invalidate_mem();
end
+ default: begin
+ `uvm_error(`gfn, $sformatf("Undefined initialization scheme - %s", scheme.name()))
+ end
endcase
endfunction : flash_mem_bkdr_init
@@ -118,16 +132,15 @@
// TODO: add support for partition.
virtual function void flash_mem_bkdr_read(flash_op_t flash_op, ref data_q_t data);
flash_mem_addr_attrs addr_attrs = new(flash_op.addr);
- bit [TL_AW-1:0] read_addr;
if (flash_op.op == flash_ctrl_pkg::FlashOpErase) begin
case (flash_op.erase_type)
flash_ctrl_pkg::FlashErasePage: begin
- read_addr = addr_attrs.page_start_addr;
+ addr_attrs.set_attrs(addr_attrs.page_start_addr);
flash_op.num_words = FlashNumBusWordsPerPage;
end
flash_ctrl_pkg::FlashEraseBank: begin
- read_addr = 0;
+ addr_attrs.set_attrs(addr_attrs.bank * BytesPerBank);
case (flash_op.partition)
FlashPartData: begin
flash_op.num_words = FlashNumBusWordsPerBank;
@@ -152,20 +165,18 @@
`uvm_fatal(`gfn, $sformatf("Invalid erase_type: %0s", flash_op.erase_type.name()))
end
endcase
- end else begin // FlashOpProgram, FlashOpRead
- read_addr = addr_attrs.bank_addr;
end
data.delete();
for (int i = 0; i < flash_op.num_words; i++) begin
- data[i] = mem_bkdr_util_h[flash_op.partition][addr_attrs.bank].read32(read_addr);
+ data[i] = mem_bkdr_util_h[flash_op.partition][addr_attrs.bank].read32(addr_attrs.bank_addr);
`uvm_info(`gfn, $sformatf(
"flash_mem_bkdr_read: partition = %s , {%s} = 0x%0h",
flash_op.partition.name(),
addr_attrs.sprint(),
data[i]
), UVM_MEDIUM)
- read_addr += TL_DBW;
+ addr_attrs.incr(TL_DBW);
end
endfunction : flash_mem_bkdr_read
@@ -177,7 +188,7 @@
virtual function void flash_mem_bkdr_write(flash_op_t flash_op, flash_mem_init_e scheme,
data_q_t data = {});
flash_mem_addr_attrs addr_attrs = new(flash_op.addr);
- logic [TL_DW-1:0] wr_data;
+ data_4s_t wr_data;
// Randomize the lower half-word (if Xs) if the first half-word written in the below loop is
// corresponding upper half-word.
@@ -202,7 +213,7 @@
endcase
for (int i = 0; i < flash_op.num_words; i++) begin
- logic [TL_DW-1:0] loc_data = (scheme == FlashMemInitCustom) ? data[i] :
+ data_4s_t loc_data = (scheme == FlashMemInitCustom) ? data[i] :
(scheme == FlashMemInitRandomize) ? $urandom() : wr_data;
_flash_full_write(flash_op.partition, addr_attrs.bank, addr_attrs.bank_addr, loc_data);
@@ -227,17 +238,14 @@
//
function void _flash_full_write(flash_dv_part_e partition, uint bank,
// bus word aligned address
- bit [TL_AW-1:0] addr,
- bit [TL_DW-1:0] wr_data);
+ addr_t addr,
+ data_t wr_data);
// read back the full flash word
logic [flash_ctrl_pkg::DataWidth-1:0] data;
logic [7:0] intg_data;
logic is_upper = addr[flash_ctrl_pkg::DataByteWidth-1];
- logic [TL_AW-1:0] aligned_addr = addr;
-
- // update memory in the scoreboard
- write_data_all_part(partition, {bank,addr}, wr_data);
+ addr_t aligned_addr = addr;
if (is_upper) begin
aligned_addr = {addr[TL_AW-1:FlashDataByteWidth], {FlashDataByteWidth{1'b0}}};
@@ -259,7 +267,13 @@
// program fully via backdoor
mem_bkdr_util_h[partition][bank].write64(aligned_addr, {intg_data[3:0], data});
- endfunction
+ // Update scoreboard memory model with this back-door write
+ if (scb_check) begin
+ write_data_all_part(.part(partition), .addr({bank, addr[FlashMemAddrPageMsbBit:0]}),
+ .is_front_door(1'b0), .data(wr_data));
+ end
+
+ endfunction : _flash_full_write
// Helper function that randomizes the half-word at the given address if unknown.
@@ -269,8 +283,8 @@
// unknown. This is needed because the flash_ctrl RTL internally fetches full words. This method
// randomizes the data at the given address via backdoor.
function void _randomize_uninitialized_half_word(flash_dv_part_e partition, uint bank,
- bit [TL_AW-1:0] addr);
- logic [TL_DW-1:0] data = mem_bkdr_util_h[partition][bank].read32(addr);
+ addr_t addr);
+ data_4s_t data = mem_bkdr_util_h[partition][bank].read32(addr);
if ($isunknown(data)) begin
`DV_CHECK_STD_RANDOMIZE_FATAL(data)
`uvm_info(`gfn, $sformatf("Data at 0x%0h is Xs, writing random 0x%0h", addr, data), UVM_HIGH)
@@ -346,7 +360,7 @@
), UVM_MEDIUM)
for (int i = 0; i < num_words; i++) begin
- logic [TL_DW-1:0] data;
+ data_4s_t data;
data = mem_bkdr_util_h[flash_op.partition][addr_attrs.bank].read32(erase_check_addr);
`uvm_info(`gfn, $sformatf(
{
@@ -378,10 +392,15 @@
return exp_data;
endfunction : calculate_expected_data
- virtual function void write_data_all_part(flash_dv_part_e part, bit [TL_AW-1:0] addr,
- ref bit [TL_DW-1:0] data);
- `uvm_info(`gfn, $sformatf("WR SCB MEM part: %0s addr:%0h data:0x%0h", part.name, addr, data),
- UVM_HIGH)
+ // Writing data to the scoreboard memory model, this writes one word of data to the selected
+ // address in the selected partition.
+ // is_front_door added to indicate if this method called by front-door
+ // write (program transaction), which is the default, or by back-door methods.
+ // This is required for extending env.
+ virtual function void write_data_all_part(flash_dv_part_e part, addr_t addr,
+ bit is_front_door = 1'b1, ref data_t data);
+ `uvm_info(`gfn, $sformatf("WRITE SCB MEM part: %0s addr:%0h data:0x%0h",
+ part.name, addr, data), UVM_HIGH)
case (part)
FlashPartData: scb_flash_data[addr] = data;
FlashPartInfo: scb_flash_info[addr] = data;
@@ -401,10 +420,10 @@
// Task for set scb memory
virtual function set_scb_mem(int bkd_num_words, flash_dv_part_e bkd_partition,
- bit [TL_AW-1:0] write_bkd_addr,flash_scb_wr_e val_type,
+ addr_t write_bkd_addr,flash_scb_wr_e val_type,
data_b_t custom_val = {});
- bit [TL_AW-1:0] wr_bkd_addr;
- bit [TL_DW-1:0] wr_value;
+ addr_t wr_bkd_addr;
+ data_t wr_value;
`uvm_info(`gfn, $sformatf(
"SET SCB MEM TEST part: %0s addr:%0h data:0x%0h num: %0d",
@@ -435,7 +454,8 @@
wr_value,
bkd_num_words
), UVM_HIGH)
- write_data_all_part(bkd_partition, wr_bkd_addr, wr_value);
+ write_data_all_part(.part(bkd_partition), .addr(wr_bkd_addr), .is_front_door(1'b0),
+ .data(wr_value));
wr_bkd_addr = wr_bkd_addr + 4;
end
endfunction : set_scb_mem
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv
index 4dec2bc..cd66bd0 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv
@@ -182,19 +182,28 @@
mubi4_t he_en; // enable high endurance
} flash_bank_mp_info_page_cfg_t;
+ // 2-states flash data type
+ typedef bit [TL_DW-1:0] data_t;
+ // 4-states flash data type
+ typedef logic [TL_DW-1:0] data_4s_t;
+ // flash address type
+ typedef bit [TL_AW-1:0] addr_t;
+ // Queue of 4-states data words
+ typedef data_4s_t data_q_t[$];
+ // Queue of 2-states data words
+ typedef data_t data_b_t[$];
+ // Array of 2-states data words indexed with flash addresses.
+ // Useful for the flash model.
+ typedef data_t data_model_t[addr_t];
+
typedef struct packed {
flash_dv_part_e partition; // data or one of the info partitions
flash_erase_e erase_type; // erase page or the whole bank
flash_op_e op; // read / program or erase
uint num_words; // number of words to read or program (TL_DW)
- bit [TL_AW-1:0] addr; // starting addr for the op
+ addr_t addr; // starting addr for the op
} flash_op_t;
- // Data queue for flash transactions
- typedef logic [TL_DW-1:0] data_q_t[$];
- typedef bit [TL_DW-1:0] data_b_t[$];
- typedef bit [TL_DW-1:0] data_t;
- typedef bit [TL_AW-1:0] addr_t;
parameter uint ALL_ZEROS = 32'h0000_0000;
parameter uint ALL_ONES = 32'hffff_ffff;
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv
index b87ca21..02e24e0 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_scoreboard.sv
@@ -40,7 +40,7 @@
uvm_tlm_analysis_fifo #(tl_seq_item) eflash_tl_d_chan_fifo;
// utility function to word-align an input TL address
- function bit [TL_AW-1:0] word_align_addr(bit [TL_AW-1:0] addr);
+ function addr_t word_align_addr(addr_t addr);
return {addr[TL_AW-1:2], 2'b00};
endfunction
@@ -172,7 +172,7 @@
write_allowed(part, wr_addr);
`uvm_info(`gfn, $sformatf("wr_access: 0x%0b wr_addr: 0x%0h", wr_access, wr_addr), UVM_LOW)
if (wr_access) begin
- cfg.write_data_all_part(part, wr_addr, item.a_data);
+ cfg.write_data_all_part(.part(part), .addr(wr_addr), .data(item.a_data));
end
if (idx_wr == num_wr) begin
idx_wr = 0;
@@ -348,8 +348,8 @@
end
endfunction
- virtual function void check_rd_data(flash_dv_part_e part, bit [TL_AW-1:0] addr,
- ref bit [TL_DW-1:0] data);
+ virtual function void check_rd_data(flash_dv_part_e part, addr_t addr,
+ ref data_t data);
case (part)
FlashPartData: begin
check_rd_part(cfg.scb_flash_data, addr, data);
@@ -367,7 +367,7 @@
endcase
endfunction
- virtual function void erase_data(flash_dv_part_e part, bit [TL_AW-1:0] addr, bit sel);
+ virtual function void erase_data(flash_dv_part_e part, addr_t addr, bit sel);
case (part)
FlashPartData: begin
erase_page_bank(NUM_BK_DATA_WORDS, addr, sel, cfg.scb_flash_data);
@@ -397,7 +397,7 @@
endfunction
- virtual task write_allowed(ref flash_dv_part_e part, ref bit [TL_AW-1:0] in_addr);
+ virtual task write_allowed(ref flash_dv_part_e part, ref addr_t in_addr);
bit en;
bit prog_en;
bit prog_en_def;
@@ -458,7 +458,7 @@
endcase
endtask
- virtual task read_allowed(ref flash_dv_part_e part, ref bit [TL_AW-1:0] in_rd_addr);
+ virtual task read_allowed(ref flash_dv_part_e part, ref addr_t in_rd_addr);
bit en;
bit read_en;
bit read_en_def;
@@ -519,7 +519,7 @@
endtask
virtual task erase_allowed(ref flash_dv_part_e part, bit erase_sel,
- ref bit [TL_AW-1:0] in_erase_addr, bit [1:0] bk_en);
+ ref addr_t in_erase_addr, bit [1:0] bk_en);
bit en;
bit erase_en;
bit erase_en_def;
@@ -584,8 +584,8 @@
end
endtask
- virtual function void check_rd_part(const ref data_t exp_data_part[addr_t],
- bit [TL_AW-1:0] addr, ref bit [TL_DW-1:0] data);
+ virtual function void check_rd_part(const ref data_model_t exp_data_part,
+ addr_t addr, ref data_t data);
if (exp_data_part.exists(addr)) begin
`uvm_info(
`gfn, $sformatf(
@@ -648,8 +648,8 @@
end
endtask
- virtual function void erase_page_bank(int num_bk_words, bit [TL_AW-1:0] addr, bit sel,
- ref data_t exp_part[addr_t]);
+ virtual function void erase_page_bank(int num_bk_words, addr_t addr, bit sel,
+ ref data_model_t exp_part);
int num_wr;
if (sel) begin // bank sel
num_wr = num_bk_words;
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv
index e0d13d7..a651ac1 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_seq_cfg.sv
@@ -36,12 +36,6 @@
uint mp_region_he_en_pc;
uint mp_region_max_pages;
- // mem for scoreboard
- data_t scb_flash_data [addr_t] = '{default: 1};
- data_t scb_flash_info [addr_t] = '{default: 1};
- data_t scb_flash_info1 [addr_t] = '{default: 1};
- data_t scb_flash_info2 [addr_t] = '{default: 1};
-
// Knob to control bank level erasability.
uint bank_erase_en_pc;
@@ -87,7 +81,7 @@
// Chances to start flash with all 1s and not with random values (default is 30%).
uint flash_init_set_pc;
- // Set by a higher level vseq that invokes this vseq
+ // Set by a higher level vseq that invokes this vseq.
bit external_cfg;
// If pre-transaction back-door memory preperation isn't needed, set do_tran_prep_mem to 0.
diff --git a/hw/ip/flash_ctrl/dv/env/flash_mem_addr_attrs.sv b/hw/ip/flash_ctrl/dv/env/flash_mem_addr_attrs.sv
index 503b7cc..385e961 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_mem_addr_attrs.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_mem_addr_attrs.sv
@@ -5,25 +5,25 @@
// Provides abstraction for mapping a flash memory address in flash organization.
class flash_mem_addr_attrs;
- bit [TL_AW-1:0] addr; // Input addr, bus-word aligned.
- bit [TL_AW-1:0] bank_addr; // Addr within the bank, bus-word aligned.
- bit [TL_AW-1:0] word_addr; // Addr within the bank, flash word aligned.
+ addr_t addr; // Input addr, bus-word aligned.
+ addr_t bank_addr; // Addr within the bank, bus-word aligned.
+ addr_t word_addr; // Addr within the bank, flash word aligned.
int offset; // Byte offset within the flash word.
- bit [TL_AW-1:0] bank_start_addr; // Start addr of the bank (bus word aligned).
- bit [TL_AW-1:0] page_start_addr; // Start addr of the page within the bank.
+ addr_t bank_start_addr; // Start addr of the bank (bus word aligned).
+ addr_t page_start_addr; // Start addr of the page within the bank.
uint bank; // The bank the address belongs to.
uint page; // The page within the bank.
uint line; // The word line within the page.
uint byte_offset; // Byte offset within the flash word.
- function new(bit [TL_AW-1:0] addr = 0);
+ function new(addr_t addr = 0);
set_attrs(addr);
endfunction
// Set attributes from a sample input addr.
- function void set_attrs(bit [TL_AW-1:0] addr);
+ function void set_attrs(addr_t addr);
this.addr = {addr[TL_AW-1:TL_SZW], {TL_SZW{1'b0}}};
bank_addr = this.addr[FlashMemAddrPageMsbBit : 0];
word_addr = {bank_addr[TL_AW-1:FlashDataByteWidth], {FlashDataByteWidth{1'b0}}};
@@ -38,7 +38,7 @@
byte_offset = addr[FlashDataByteWidth-1 : 0];
endfunction
- function void incr(bit [TL_AW-1:0] offset);
+ function void incr(addr_t offset);
// TODO: Check for overflow
set_attrs(addr + offset);
endfunction
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv
index 23556b0..06283f7 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv
@@ -316,10 +316,10 @@
// Task to perform a direct Flash read at the specified location
virtual task do_direct_read(
- input bit [TL_AW-1:0] addr, input bit [TL_DBW-1:0] mask = get_rand_contiguous_mask(),
+ input addr_t addr, input bit [TL_DBW-1:0] mask = get_rand_contiguous_mask(),
input bit blocking = $urandom_range(0, 1), input bit check_rdata = 0,
- input bit [TL_DW-1:0] exp_rdata = '0, input mubi4_t instr_type = MuBi4False,
- output logic [TL_DW-1:0] rdata, input bit exp_err_rsp = 1'b0);
+ input data_t exp_rdata = '0, input mubi4_t instr_type = MuBi4False,
+ output data_4s_t rdata, input bit exp_err_rsp = 1'b0);
tl_access(.addr(addr), .write(1'b0), .data(rdata), .mask(mask), .blocking(blocking),
.check_exp_data(check_rdata), .exp_data(exp_rdata), .compare_mask(mask),
.instr_type(instr_type), .exp_err_rsp(exp_err_rsp),
@@ -336,7 +336,7 @@
// Local Signals
bit poll_fifo_status;
- logic [TL_DW-1:0] exp_data[$];
+ data_q_t exp_data;
flash_op_t flash_op;
// Flash Operation Assignments
@@ -455,7 +455,6 @@
endtask : lc_ctrl_if_rst
// Simple Model For The OTP Key Seeds
- // Communicates with the TB via the flash_ctrl_vif
virtual task otp_model();
`uvm_info(`gfn, "Starting OTP Model ...", UVM_LOW)
@@ -581,7 +580,7 @@
// Local Variables
bit poll_fifo_status;
- logic [TL_DW-1:0] exp_data[$];
+ data_q_t exp_data;
flash_op_t flash_op;
data_q_t flash_op_rdata;
int match_cnt;
@@ -721,9 +720,9 @@
int num;
int num_full;
int num_part;
- logic [TL_DW-1:0] fifo_data;
- logic [TL_AW-1:0] flash_addr;
- logic [TL_DW-1:0] exp_data[$];
+ data_4s_t fifo_data;
+ addr_t flash_addr;
+ data_q_t exp_data;
flash_op_t flash_op_copy;
data_q_t data_copy;
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_erase_suspend_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_erase_suspend_vseq.sv
index 17365da..429b277 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_erase_suspend_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_erase_suspend_vseq.sv
@@ -182,7 +182,7 @@
data_q_t flash_rd_data;
uvm_reg_data_t data;
- localparam bit [TL_DW-1:0] ALL_ONES = {TL_DW{1'b1}};
+ localparam data_t ALL_ONES = {TL_DW{1'b1}};
virtual task body();
repeat (cfg.seq_cfg.max_num_trans) begin
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_fetch_code_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_fetch_code_vseq.sv
index 3b19ea6..812735a 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_fetch_code_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_fetch_code_vseq.sv
@@ -299,9 +299,9 @@
virtual task check_code_access(input bit opt);
// Local Variables
- bit [TL_AW-1:0] read_addr;
- bit [TL_DW-1:0] rdata;
- bit [TL_DW-1:0] rdata_unused;
+ addr_t read_addr;
+ data_t rdata;
+ data_t rdata_unused;
// Note : opt 'CODE_FETCH_ALLOWED' - Access Allowed, 'CODE_FETCH_DENIED' - Access Denied
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_full_mem_access_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_full_mem_access_vseq.sv
index 594ac21..ab31a58 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_full_mem_access_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_full_mem_access_vseq.sv
@@ -20,7 +20,7 @@
rand flash_op_t flash_op;
rand bit selected_bank;
- bit [TL_AW-1:0] bank_start_addr;
+ addr_t bank_start_addr;
// Memory protection regions settings.
flash_mp_region_cfg_t mp_regions[flash_ctrl_pkg::MpRegions];
@@ -182,7 +182,7 @@
virtual task do_direct_rd();
bit [TL_AW-1:0] read_addr;
bit [TL_AW-1:0] start_addr;
- logic [TL_DW-1:0] rdata;
+ data_4s_t rdata;
start_addr = bank_start_addr;
cfg.dir_rd_in_progress = 1'b1;
for (int i = 0; i < NUM_BK_DATA_WORDS; i++) begin
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_host_dir_rd_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_host_dir_rd_vseq.sv
index 24440a8..07a1282 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_host_dir_rd_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_host_dir_rd_vseq.sv
@@ -52,7 +52,7 @@
rand data_q_t flash_op_data;
// Single direct read data
- bit [TL_DW-1:0] flash_rd_one_data;
+ data_t flash_rd_one_data;
constraint flash_op_data_c {
solve flash_op before flash_op_data;
@@ -138,7 +138,7 @@
constraint default_region_ecc_en_c {default_region_ecc_en == MuBi4False;}
bit [TL_AW-1:0] read_addr;
- logic [TL_DW-1:0] rdata;
+ data_4s_t rdata;
virtual task body();
repeat (num_trans) begin
// Randomize self
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_phy_arb_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_phy_arb_vseq.sv
index 3d1b548..663fa7e 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_phy_arb_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_phy_arb_vseq.sv
@@ -233,12 +233,12 @@
constraint default_region_ecc_en_c {default_region_ecc_en == MuBi4False;}
- bit [TL_AW-1:0] read_addr;
+ addr_t read_addr;
// Single direct read data
- bit [TL_DW-1:0] flash_rd_one_data;
+ data_t flash_rd_one_data;
- localparam bit [TL_DW-1:0] ALL_ONES = {TL_DW{1'b1}};
+ localparam data_t ALL_ONES = {TL_DW{1'b1}};
virtual task body();
@@ -276,7 +276,7 @@
cfg.flash_mem_bkdr_init(flash_op_host_rd.partition, FlashMemInitInvalidate);
if (flash_op.op == flash_ctrl_pkg::FlashOpProgram) begin
cfg.flash_mem_bkdr_write(.flash_op(flash_op), .scheme(FlashMemInitSet));
- end else begin
+ end else if (flash_op.op == flash_ctrl_pkg::FlashOpRead) begin
cfg.flash_mem_bkdr_write(.flash_op(flash_op), .scheme(FlashMemInitRandomize));
end
cfg.flash_mem_bkdr_write(.flash_op(flash_op_host_rd), .scheme(FlashMemInitRandomize));
@@ -301,7 +301,7 @@
cfg.flash_mem_bkdr_init(flash_op_host_rd.partition, FlashMemInitInvalidate);
if (flash_op.op == flash_ctrl_pkg::FlashOpProgram) begin
cfg.flash_mem_bkdr_write(.flash_op(flash_op), .scheme(FlashMemInitSet));
- end else begin
+ end else if (flash_op.op == flash_ctrl_pkg::FlashOpRead) begin
cfg.flash_mem_bkdr_write(.flash_op(flash_op), .scheme(FlashMemInitRandomize));
end
cfg.flash_mem_bkdr_write(.flash_op(flash_op_host_rd), .scheme(FlashMemInitRandomize));
@@ -350,34 +350,34 @@
fork
begin
// host read data and init of selected chunk of memory
- host_read_op_data(flash_op_host_rd);
+ host_read_data(flash_op_host_rd);
end
begin
// controller read, program or erase
if (flash_op.op == flash_ctrl_pkg::FlashOpRead) begin
- controller_read_op_data(flash_op);
+ controller_read_data(flash_op);
end else if (flash_op.op == flash_ctrl_pkg::FlashOpProgram) begin
controller_program_data(flash_op, flash_op_data);
end else begin //flash_op.op == flash_ctrl_pkg::FlashOpErase
- controller_program_erase(flash_op);
+ controller_erase_data(flash_op);
end
end
join;
endtask : do_operations
// host read data.
- virtual task host_read_op_data(flash_op_t flash_op);
- logic [TL_DW-1:0] rdata;
+ virtual task host_read_data(flash_op_t flash_op);
+ data_4s_t rdata;
for (int j = 0; j < flash_op.num_words; j++) begin
read_addr = flash_op.addr + 4 * j;
do_direct_read(.addr(read_addr), .mask('1), .blocking(cfg.block_host_rd), .check_rdata(0),
.rdata(rdata));
cfg.clk_rst_vif.wait_clks($urandom_range(0, 10));
end
- endtask : host_read_op_data
+ endtask : host_read_data
// Controller read data.
- virtual task controller_read_op_data(flash_op_t flash_op);
+ virtual task controller_read_data(flash_op_t flash_op);
flash_rd_data.delete();
flash_ctrl_start_op(flash_op);
flash_ctrl_read(flash_op.num_words, flash_rd_data, poll_fifo_status);
@@ -385,7 +385,7 @@
`uvm_info(`gfn, $sformatf("FLASH OP READ DATA: %0p", flash_rd_data), UVM_HIGH)
cfg.flash_mem_bkdr_read_check(flash_op, flash_rd_data);
cfg.clk_rst_vif.wait_clks($urandom_range(0, 10));
- endtask : controller_read_op_data
+ endtask : controller_read_data
// Controller program data.
virtual task controller_program_data(flash_op_t flash_op, data_q_t flash_op_data);
@@ -400,17 +400,17 @@
endtask : controller_program_data
// Controller erase data.
- virtual task controller_program_erase(flash_op_t flash_op);
+ virtual task controller_erase_data(flash_op_t flash_op);
data_q_t exp_data;
exp_data = cfg.calculate_expected_data(flash_op, flash_op_data);
flash_ctrl_start_op(flash_op);
wait_flash_op_done(.timeout_ns(cfg.seq_cfg.erase_timeout_ns));
`uvm_info(`gfn, $sformatf("FLASH OP ERASE DATA DONE"), UVM_HIGH)
cfg.flash_mem_bkdr_erase_check(flash_op, exp_data);
- endtask : controller_program_erase
+ endtask : controller_erase_data
virtual task do_arb();
- logic [TL_DW-1:0] rdata;
+ data_4s_t rdata;
data_q_t exp_data;
// setting non blocking host reads
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_rd_buff_evict_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_rd_buff_evict_vseq.sv
index 1333ab3..3b607e7 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_rd_buff_evict_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_rd_buff_evict_vseq.sv
@@ -54,7 +54,7 @@
data_q_t flash_rd_data;
// Single host read data
- bit [TL_DW-1:0] flash_rd_one_data;
+ data_t flash_rd_one_data;
constraint flash_op_data_c {
solve flash_op before flash_op_data;
@@ -130,9 +130,9 @@
};
}
- bit [TL_AW-1:0] read_addr;
- logic [TL_DW-1:0] exp_data[$];
- logic [TL_DW-1:0] all_ones = {TL_DW{1'b1}};
+ addr_t read_addr;
+ data_q_t exp_data;
+ data_4s_t all_ones = {TL_DW{1'b1}};
task body();
@@ -389,7 +389,7 @@
// host read data.
virtual task host_read_op_data(flash_op_t flash_op);
- logic [TL_DW-1:0] rdata;
+ data_4s_t rdata;
exp_data.delete();
for (int j = 0; j < flash_op.num_words; j++) begin
read_addr = flash_op.addr + 4 * j;
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_smoke_hw_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_smoke_hw_vseq.sv
index 3999672..9dffe0c 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_smoke_hw_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_smoke_hw_vseq.sv
@@ -20,8 +20,8 @@
endfunction
task body();
- logic [TL_DW-1:0] rdata;
- logic [TL_DW-1:0] exp_data[$];
+ data_4s_t rdata;
+ data_q_t exp_data;
int flash_depth = flash_ctrl_reg_pkg::BytesPerBank / 4;
