[dif/clkmgr] Integrate autogen'd DIF artifacts into src tree.
This commit partially addresses #8142. Specifically it:
1. deprecates existing (manually implemented) **Clock Manager**
specific DIF return codes and toggle types,
2. integrates the auto-generated **Clock Manager** DIFs into meson build
targets,
3. refactors all existing source code to make use of the new shared DIF
types and error codes, and
4. separates the MMIO base address for the IP from the
`dif_clkmgr_params_t` struct and updates DIF prototypes to take in
and extra params struct arg to stay consistent with the Alert Handler
DIFs, as described in #8409.
This continues the long-term goal of auto-generating several DIF
components across all IPs, as described in #8142.
Signed-off-by: Timothy Trippel <ttrippel@google.com>
diff --git a/hw/top_englishbreakfast/util/sw_sources.patch b/hw/top_englishbreakfast/util/sw_sources.patch
index 9a53f13..913074d 100644
--- a/hw/top_englishbreakfast/util/sw_sources.patch
+++ b/hw/top_englishbreakfast/util/sw_sources.patch
@@ -75,7 +75,7 @@
simple_serial_process_packet();
}
diff --git a/sw/device/sca/lib/sca.c b/sw/device/sca/lib/sca.c
-index e894f1793..5629a15d8 100644
+index 4a431b9ea..fcfcee1ab 100644
--- a/sw/device/sca/lib/sca.c
+++ b/sw/device/sca/lib/sca.c
@@ -56,7 +56,6 @@ enum {
@@ -102,7 +102,7 @@
}
/**
-@@ -148,30 +143,11 @@ void handler_irq_timer(void) {
+@@ -148,29 +143,10 @@ void handler_irq_timer(void) {
* @param disable Set of peripherals to disable.
*/
void sca_disable_peripherals(sca_peripherals_t disable) {
@@ -127,33 +127,32 @@
-
// Disable HMAC, KMAC, OTBN and USB clocks through CLKMGR DIF.
const dif_clkmgr_params_t clkmgr_params = {
- .base_addr = mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR),
.last_gateable_clock = CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
- .last_hintable_clock = CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT};
+ .last_hintable_clock = CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT};
dif_clkmgr_t clkmgr;
- IGNORE_RESULT(dif_clkmgr_init(clkmgr_params, &clkmgr));
-
-@@ -185,19 +161,6 @@ void sca_disable_peripherals(sca_peripherals_t disable) {
- &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT,
- kDifClkmgrToggleDisabled));
+ IGNORE_RESULT(
+ dif_clkmgr_init(mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR),
+@@ -186,19 +162,6 @@ void sca_disable_peripherals(sca_peripherals_t disable) {
+ &clkmgr, clkmgr_params, CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT,
+ kDifToggleDisabled));
}
- if (disable & kScaPeripheralKmac) {
- IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
-- &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_KMAC_HINT_BIT,
-- kDifClkmgrToggleDisabled));
+- &clkmgr, clkmgr_params, CLKMGR_CLK_HINTS_CLK_MAIN_KMAC_HINT_BIT,
+- kDifToggleDisabled));
- }
- if (disable & kScaPeripheralOtbn) {
- IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
-- &clkmgr, CLKMGR_CLK_HINTS_CLK_IO_DIV4_OTBN_HINT_BIT,
-- kDifClkmgrToggleDisabled));
+- &clkmgr, clkmgr_params, CLKMGR_CLK_HINTS_CLK_IO_DIV4_OTBN_HINT_BIT,
+- kDifToggleDisabled));
- IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
-- &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT,
-- kDifClkmgrToggleDisabled));
+- &clkmgr, clkmgr_params, CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT,
+- kDifToggleDisabled));
- }
if (disable & kScaPeripheralUsb) {
IGNORE_RESULT(dif_clkmgr_gateable_clock_set_enabled(
- &clkmgr, CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
+ &clkmgr, clkmgr_params, CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
diff --git a/sw/device/tests/aes_smoketest.c b/sw/device/tests/aes_smoketest.c
index 1a5fef16c..214e08151 100644
--- a/sw/device/tests/aes_smoketest.c
@@ -177,7 +176,7 @@
CHECK_DIF_OK(
dif_aes_init(mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR), &aes));
diff --git a/sw/device/tests/meson.build b/sw/device/tests/meson.build
-index d9260ca0f..ff7e3ee0b 100644
+index 96803744e..27e3e2727 100644
--- a/sw/device/tests/meson.build
+++ b/sw/device/tests/meson.build
@@ -207,7 +207,6 @@ aes_smoketest_lib = declare_dependency(
diff --git a/sw/device/lib/dif/autogen/meson.build b/sw/device/lib/dif/autogen/meson.build
index 223f887..2e02360 100644
--- a/sw/device/lib/dif/autogen/meson.build
+++ b/sw/device/lib/dif/autogen/meson.build
@@ -2,13 +2,13 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-# Autogen Reset Manager DIF library
-sw_lib_dif_autogen_rstmgr = declare_dependency(
+# Autogen Clock Manager DIF library
+sw_lib_dif_autogen_clkmgr = declare_dependency(
link_with: static_library(
- 'sw_lib_dif_autogen_rstmgr',
+ 'sw_lib_dif_autogen_clkmgr',
sources: [
- hw_ip_rstmgr_reg_h,
- 'dif_rstmgr_autogen.c',
+ hw_ip_clkmgr_reg_h,
+ 'dif_clkmgr_autogen.c',
],
dependencies: [
sw_lib_mmio,
@@ -170,6 +170,20 @@
)
)
+# Autogen Reset Manager DIF library
+sw_lib_dif_autogen_rstmgr = declare_dependency(
+ link_with: static_library(
+ 'sw_lib_dif_autogen_rstmgr',
+ sources: [
+ hw_ip_rstmgr_reg_h,
+ 'dif_rstmgr_autogen.c',
+ ],
+ dependencies: [
+ sw_lib_mmio,
+ ],
+ )
+)
+
# Autogen UART DIF library
sw_lib_dif_autogen_uart = declare_dependency(
link_with: static_library(
diff --git a/sw/device/lib/dif/dif_clkmgr.c b/sw/device/lib/dif/dif_clkmgr.c
index 5dac36c..18f92fb 100644
--- a/sw/device/lib/dif/dif_clkmgr.c
+++ b/sw/device/lib/dif/dif_clkmgr.c
@@ -6,6 +6,7 @@
#include "sw/device/lib/base/bitfield.h"
#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_base.h"
#include "clkmgr_regs.h" // Generated
@@ -27,10 +28,10 @@
(params.last_hintable_clock < CLKMGR_PARAM_REG_WIDTH);
}
-dif_clkmgr_result_t dif_clkmgr_init(dif_clkmgr_params_t params,
- dif_clkmgr_t *handle) {
- if (handle == NULL) {
- return kDifClkmgrBadArg;
+dif_result_t dif_clkmgr_init(mmio_region_t base_addr,
+ dif_clkmgr_params_t params, dif_clkmgr_t *clkmgr) {
+ if (clkmgr == NULL) {
+ return kDifBadArg;
}
// TODO: For the moment, `last_hintable_clock` and `last_gateable_clock` has
@@ -38,111 +39,112 @@
// https://github.com/lowRISC/opentitan/issues/4201
if (params.last_gateable_clock >= CLKMGR_PARAM_REG_WIDTH ||
params.last_hintable_clock >= CLKMGR_PARAM_REG_WIDTH) {
- return kDifClkmgrBadArg;
+ return kDifBadArg;
}
- handle->params = params;
- return kDifClkmgrOk;
+ clkmgr->base_addr = base_addr;
+
+ return kDifOk;
}
-dif_clkmgr_result_t dif_clkmgr_gateable_clock_get_enabled(
- const dif_clkmgr_t *handle, dif_clkmgr_gateable_clock_t clock,
- bool *is_enabled) {
- if (handle == NULL || is_enabled == NULL ||
- !clkmgr_valid_gateable_clock(handle->params, clock)) {
- return kDifClkmgrBadArg;
+dif_result_t dif_clkmgr_gateable_clock_get_enabled(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_params_t params,
+ dif_clkmgr_gateable_clock_t clock, bool *is_enabled) {
+ if (clkmgr == NULL || is_enabled == NULL ||
+ !clkmgr_valid_gateable_clock(params, clock)) {
+ return kDifBadArg;
}
- uint32_t clk_enables_val = mmio_region_read32(handle->params.base_addr,
- CLKMGR_CLK_ENABLES_REG_OFFSET);
+ uint32_t clk_enables_val =
+ mmio_region_read32(clkmgr->base_addr, CLKMGR_CLK_ENABLES_REG_OFFSET);
*is_enabled = bitfield_bit32_read(clk_enables_val, clock);
- return kDifClkmgrOk;
+ return kDifOk;
}
-dif_clkmgr_result_t dif_clkmgr_gateable_clock_set_enabled(
- const dif_clkmgr_t *handle, dif_clkmgr_gateable_clock_t clock,
- dif_clkmgr_toggle_t new_state) {
- if (handle == NULL || !clkmgr_valid_gateable_clock(handle->params, clock)) {
- return kDifClkmgrBadArg;
+dif_result_t dif_clkmgr_gateable_clock_set_enabled(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_params_t params,
+ dif_clkmgr_gateable_clock_t clock, dif_toggle_t new_state) {
+ if (clkmgr == NULL || !clkmgr_valid_gateable_clock(params, clock)) {
+ return kDifBadArg;
}
bool new_clk_enables_bit;
switch (new_state) {
- case kDifClkmgrToggleEnabled:
+ case kDifToggleEnabled:
new_clk_enables_bit = true;
break;
- case kDifClkmgrToggleDisabled:
+ case kDifToggleDisabled:
new_clk_enables_bit = false;
break;
default:
- return kDifClkmgrBadArg;
+ return kDifBadArg;
}
- uint32_t clk_enables_val = mmio_region_read32(handle->params.base_addr,
- CLKMGR_CLK_ENABLES_REG_OFFSET);
+ uint32_t clk_enables_val =
+ mmio_region_read32(clkmgr->base_addr, CLKMGR_CLK_ENABLES_REG_OFFSET);
clk_enables_val =
bitfield_bit32_write(clk_enables_val, clock, new_clk_enables_bit);
- mmio_region_write32(handle->params.base_addr, CLKMGR_CLK_ENABLES_REG_OFFSET,
+ mmio_region_write32(clkmgr->base_addr, CLKMGR_CLK_ENABLES_REG_OFFSET,
clk_enables_val);
- return kDifClkmgrOk;
+ return kDifOk;
}
-dif_clkmgr_result_t dif_clkmgr_hintable_clock_get_enabled(
- const dif_clkmgr_t *handle, dif_clkmgr_hintable_clock_t clock,
- bool *is_enabled) {
- if (handle == NULL || is_enabled == NULL ||
- !clkmgr_valid_hintable_clock(handle->params, clock)) {
- return kDifClkmgrBadArg;
+dif_result_t dif_clkmgr_hintable_clock_get_enabled(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_params_t params,
+ dif_clkmgr_hintable_clock_t clock, bool *is_enabled) {
+ if (clkmgr == NULL || is_enabled == NULL ||
+ !clkmgr_valid_hintable_clock(params, clock)) {
+ return kDifBadArg;
}
- uint32_t clk_hints_val = mmio_region_read32(
- handle->params.base_addr, CLKMGR_CLK_HINTS_STATUS_REG_OFFSET);
+ uint32_t clk_hints_val =
+ mmio_region_read32(clkmgr->base_addr, CLKMGR_CLK_HINTS_STATUS_REG_OFFSET);
*is_enabled = bitfield_bit32_read(clk_hints_val, clock);
- return kDifClkmgrOk;
+ return kDifOk;
}
-dif_clkmgr_result_t dif_clkmgr_hintable_clock_set_hint(
- const dif_clkmgr_t *handle, dif_clkmgr_hintable_clock_t clock,
- dif_clkmgr_toggle_t new_state) {
- if (handle == NULL || !clkmgr_valid_hintable_clock(handle->params, clock)) {
- return kDifClkmgrBadArg;
+dif_result_t dif_clkmgr_hintable_clock_set_hint(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_params_t params,
+ dif_clkmgr_hintable_clock_t clock, dif_toggle_t new_state) {
+ if (clkmgr == NULL || !clkmgr_valid_hintable_clock(params, clock)) {
+ return kDifBadArg;
}
bool new_clk_hints_bit;
switch (new_state) {
- case kDifClkmgrToggleEnabled:
+ case kDifToggleEnabled:
new_clk_hints_bit = true;
break;
- case kDifClkmgrToggleDisabled:
+ case kDifToggleDisabled:
new_clk_hints_bit = false;
break;
default:
- return kDifClkmgrBadArg;
+ return kDifBadArg;
}
uint32_t clk_hints_val =
- mmio_region_read32(handle->params.base_addr, CLKMGR_CLK_HINTS_REG_OFFSET);
+ mmio_region_read32(clkmgr->base_addr, CLKMGR_CLK_HINTS_REG_OFFSET);
clk_hints_val = bitfield_bit32_write(clk_hints_val, clock, new_clk_hints_bit);
- mmio_region_write32(handle->params.base_addr, CLKMGR_CLK_HINTS_REG_OFFSET,
+ mmio_region_write32(clkmgr->base_addr, CLKMGR_CLK_HINTS_REG_OFFSET,
clk_hints_val);
- return kDifClkmgrOk;
+ return kDifOk;
}
-dif_clkmgr_result_t dif_clkmgr_hintable_clock_get_hint(
- const dif_clkmgr_t *handle, dif_clkmgr_hintable_clock_t clock,
- bool *hinted_is_enabled) {
- if (handle == NULL || hinted_is_enabled == NULL ||
- !clkmgr_valid_hintable_clock(handle->params, clock)) {
- return kDifClkmgrBadArg;
+dif_result_t dif_clkmgr_hintable_clock_get_hint(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_params_t params,
+ dif_clkmgr_hintable_clock_t clock, bool *hinted_is_enabled) {
+ if (clkmgr == NULL || hinted_is_enabled == NULL ||
+ !clkmgr_valid_hintable_clock(params, clock)) {
+ return kDifBadArg;
}
uint32_t clk_hints_val =
- mmio_region_read32(handle->params.base_addr, CLKMGR_CLK_HINTS_REG_OFFSET);
+ mmio_region_read32(clkmgr->base_addr, CLKMGR_CLK_HINTS_REG_OFFSET);
*hinted_is_enabled = bitfield_bit32_read(clk_hints_val, clock);
- return kDifClkmgrOk;
+ return kDifOk;
}
diff --git a/sw/device/lib/dif/dif_clkmgr.h b/sw/device/lib/dif/dif_clkmgr.h
index cf759a0..ebf5ad6 100644
--- a/sw/device/lib/dif/dif_clkmgr.h
+++ b/sw/device/lib/dif/dif_clkmgr.h
@@ -15,6 +15,9 @@
#include "sw/device/lib/base/macros.h"
#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_base.h"
+
+#include "sw/device/lib/dif/autogen/dif_clkmgr_autogen.h"
#ifdef __cplusplus
extern "C" {
@@ -38,23 +41,6 @@
typedef uint32_t dif_clkmgr_hintable_clock_t;
/**
- * A toggle state: enabled, or disabled.
- *
- * This enum may be used instead of a `bool` when describing an enabled/disabled
- * state.
- */
-typedef enum dif_clkmgr_toggle {
- /*
- * The "enabled" state.
- */
- kDifClkmgrToggleEnabled,
- /**
- * The "disabled" state.
- */
- kDifClkmgrToggleDisabled,
-} dif_clkmgr_toggle_t;
-
-/**
* Hardware instantiation parameters for a clock manager.
*
* This struct describes information about the underlying hardware instance that
@@ -63,10 +49,6 @@
*/
typedef struct dif_clkmgr_params {
/**
- * The base address for the clock manager hardware registers.
- */
- mmio_region_t base_addr;
- /**
* The last index of gateable clocks being managed by this clock manager.
*/
dif_clkmgr_gateable_clock_t last_gateable_clock;
@@ -77,73 +59,46 @@
} dif_clkmgr_params_t;
/**
- * A handle to a clock manager.
- *
- * This type should be treated as opaque by users.
- */
-typedef struct dif_clkmgr {
- dif_clkmgr_params_t params;
-} dif_clkmgr_t;
-
-/**
- * The result of a clock manager operation.
- */
-typedef enum dif_clkmgr_result {
- /**
- * Indicates that the operation succeeded.
- */
- kDifClkmgrOk = 0,
- /**
- * Indicates some unspecified failure.
- */
- kDifClkmgrError = 1,
- /**
- * Indicates that some parameter passed into a function failed a
- * precondition.
- *
- * When this value is returned, no hardware operations occurred.
- */
- kDifClkmgrBadArg = 2,
-} dif_clkmgr_result_t;
-
-/**
* Creates a new handle for a clock manager.
*
* This function does not actuate the hardware.
*
+ * @param base_addr Hardware instantiation base address.
* @param params Hardware instance parameters.
- * @param[out] handle Out param for the initialized handle.
+ * @param[out] clkmgr Out param for the initialized handle.
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_clkmgr_result_t dif_clkmgr_init(dif_clkmgr_params_t params,
- dif_clkmgr_t *handle);
+dif_result_t dif_clkmgr_init(mmio_region_t base_addr,
+ dif_clkmgr_params_t params, dif_clkmgr_t *clkmgr);
/**
* Check if a Gateable Clock is Enabled or Disabled.
*
- * @param handle Clock Manager Handle.
+ * @param clkmgr Clock Manager Handle.
+ * @param params Hardware instance parameters.
* @param clock Gateable Clock ID.
* @param[out] is_enabled whether the clock is enabled or not.
* @returns The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_clkmgr_result_t dif_clkmgr_gateable_clock_get_enabled(
- const dif_clkmgr_t *handle, dif_clkmgr_gateable_clock_t clock,
- bool *is_enabled);
+dif_result_t dif_clkmgr_gateable_clock_get_enabled(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_params_t params,
+ dif_clkmgr_gateable_clock_t clock, bool *is_enabled);
/**
* Enable or Disable a Gateable Clock.
*
- * @param handle Clock Manager Handle.
+ * @param clkmgr Clock Manager Handle.
+ * @param params Hardware instance parameters.
* @param clock Gateable Clock ID.
* @param new_state whether to enable or disable the clock.
* @returns The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_clkmgr_result_t dif_clkmgr_gateable_clock_set_enabled(
- const dif_clkmgr_t *handle, dif_clkmgr_gateable_clock_t clock,
- dif_clkmgr_toggle_t new_state);
+dif_result_t dif_clkmgr_gateable_clock_set_enabled(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_params_t params,
+ dif_clkmgr_gateable_clock_t clock, dif_toggle_t new_state);
/**
* Check if a Hintable Clock is Enabled or Disabled.
@@ -155,15 +110,16 @@
* To read what hint the software has given the hardware, use
* #dif_clkmgr_hintable_clock_get_hint.
*
- * @param handle Clock Manager Handle.
+ * @param clkmgr Clock Manager Handle.
+ * @param params Hardware instance parameters.
* @param clock Hintable Clock ID.
* @param[out] is_enabled whether the clock is enabled or not.
* @returns The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_clkmgr_result_t dif_clkmgr_hintable_clock_get_enabled(
- const dif_clkmgr_t *handle, dif_clkmgr_hintable_clock_t clock,
- bool *is_enabled);
+dif_result_t dif_clkmgr_hintable_clock_get_enabled(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_params_t params,
+ dif_clkmgr_hintable_clock_t clock, bool *is_enabled);
/**
* Enable or Disable a Hintable Clock.
@@ -176,15 +132,16 @@
* #dif_clkmgr_hintable_clock_get_hint. To read whether the clock is currently
* enabled or disabled, use #dif_clkmgr_hintable_clock_get_enabled.
*
- * @param handle Clock Manager Handle.
+ * @param clkmgr Clock Manager Handle.
+ * @param params Hardware instance parameters.
* @param clock Hintable Clock ID.
* @param new_state whether to enable or disable the clock.
* @returns The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_clkmgr_result_t dif_clkmgr_hintable_clock_set_hint(
- const dif_clkmgr_t *handle, dif_clkmgr_hintable_clock_t clock,
- dif_clkmgr_toggle_t new_state);
+dif_result_t dif_clkmgr_hintable_clock_set_hint(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_params_t params,
+ dif_clkmgr_hintable_clock_t clock, dif_toggle_t new_state);
/**
* Read the current Hint for a Hintable Clock.
@@ -196,16 +153,17 @@
* To read whether the clock is currently enabled or disabled, use
* #dif_clkmgr_hintable_clock_get_enabled.
*
- * @param handle Clock Manager Handle.
+ * @param clkmgr Clock Manager Handle.
+ * @param params Hardware instance parameters.
* @param clock Hintable Clock ID.
* @param[out] hinted_is_enabled the current software request (hint) for this
* clock.
* @returns The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_clkmgr_result_t dif_clkmgr_hintable_clock_get_hint(
- const dif_clkmgr_t *handle, dif_clkmgr_hintable_clock_t clock,
- bool *hinted_is_enabled);
+dif_result_t dif_clkmgr_hintable_clock_get_hint(
+ const dif_clkmgr_t *clkmgr, dif_clkmgr_params_t params,
+ dif_clkmgr_hintable_clock_t clock, bool *hinted_is_enabled);
#ifdef __cplusplus
} // extern "C"
diff --git a/sw/device/lib/dif/dif_clkmgr_unittest.cc b/sw/device/lib/dif/dif_clkmgr_unittest.cc
index 0b7860f..c9b01e3 100644
--- a/sw/device/lib/dif/dif_clkmgr_unittest.cc
+++ b/sw/device/lib/dif/dif_clkmgr_unittest.cc
@@ -27,13 +27,12 @@
class ClkMgrTest : public Test, public MmioTest {
protected:
const dif_clkmgr_params_t params_ = {
- .base_addr = dev().region(),
.last_gateable_clock = CLKMGR_CLK_ENABLES_LAST_BIT,
.last_hintable_clock = CLKMGR_CLK_HINTS_LAST_BIT};
- dif_clkmgr_t clkmgr_;
+ dif_clkmgr_t clkmgr_ = {.base_addr = dev().region()};
ClkMgrTest() {
EXPECT_EQ(CLKMGR_CLK_HINTS_LAST_BIT, CLKMGR_CLK_HINTS_STATUS_LAST_BIT);
- EXPECT_EQ(dif_clkmgr_init(params_, &clkmgr_), kDifClkmgrOk);
+ EXPECT_EQ(dif_clkmgr_init(dev().region(), params_, &clkmgr_), kDifOk);
}
};
@@ -41,21 +40,23 @@
TEST_F(InitTest, Error) {
// Null handle.
- EXPECT_EQ(dif_clkmgr_init(params_, nullptr), kDifClkmgrBadArg);
+ EXPECT_EQ(dif_clkmgr_init(dev().region(), params_, nullptr), kDifBadArg);
// Out-of-bounds last gateable clock.
{
dif_clkmgr_t clkmgr;
dif_clkmgr_params_t bad_gateable = params_;
bad_gateable.last_gateable_clock = CLKMGR_PARAM_REG_WIDTH;
- EXPECT_EQ(dif_clkmgr_init(bad_gateable, &clkmgr), kDifClkmgrBadArg);
+ EXPECT_EQ(dif_clkmgr_init(dev().region(), bad_gateable, &clkmgr),
+ kDifBadArg);
}
{
dif_clkmgr_t clkmgr;
dif_clkmgr_params_t bad_gateable = params_;
bad_gateable.last_gateable_clock =
std::numeric_limits<dif_clkmgr_gateable_clock_t>::max();
- EXPECT_EQ(dif_clkmgr_init(bad_gateable, &clkmgr), kDifClkmgrBadArg);
+ EXPECT_EQ(dif_clkmgr_init(dev().region(), bad_gateable, &clkmgr),
+ kDifBadArg);
}
// Out-of-bounds last hintable clock.
@@ -63,14 +64,16 @@
dif_clkmgr_t clkmgr;
dif_clkmgr_params_t bad_hintable = params_;
bad_hintable.last_hintable_clock = CLKMGR_PARAM_REG_WIDTH;
- EXPECT_EQ(dif_clkmgr_init(bad_hintable, &clkmgr), kDifClkmgrBadArg);
+ EXPECT_EQ(dif_clkmgr_init(dev().region(), bad_hintable, &clkmgr),
+ kDifBadArg);
}
{
dif_clkmgr_t clkmgr;
dif_clkmgr_params_t bad_hintable = params_;
bad_hintable.last_hintable_clock =
std::numeric_limits<dif_clkmgr_hintable_clock_t>::max();
- EXPECT_EQ(dif_clkmgr_init(bad_hintable, &clkmgr), kDifClkmgrBadArg);
+ EXPECT_EQ(dif_clkmgr_init(dev().region(), bad_hintable, &clkmgr),
+ kDifBadArg);
}
}
@@ -81,38 +84,38 @@
EXPECT_MASK32(CLKMGR_CLK_ENABLES_REG_OFFSET,
{{CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT, 0x1, false}});
EXPECT_EQ(dif_clkmgr_gateable_clock_set_enabled(
- &clkmgr_, CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT,
- kDifClkmgrToggleDisabled),
- kDifClkmgrOk);
+ &clkmgr_, params_, CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT,
+ kDifToggleDisabled),
+ kDifOk);
// Enable gateable clock.
EXPECT_MASK32(CLKMGR_CLK_ENABLES_REG_OFFSET,
{{CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT, 0x1, true}});
EXPECT_EQ(dif_clkmgr_gateable_clock_set_enabled(
- &clkmgr_, CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
- kDifClkmgrToggleEnabled),
- kDifClkmgrOk);
+ &clkmgr_, params_, CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
+ kDifToggleEnabled),
+ kDifOk);
}
TEST_F(GateableClockTest, SetEnabledError) {
// Null handle.
EXPECT_EQ(dif_clkmgr_gateable_clock_set_enabled(
- nullptr, CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT,
- kDifClkmgrToggleEnabled),
- kDifClkmgrBadArg);
+ nullptr, params_, CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT,
+ kDifToggleEnabled),
+ kDifBadArg);
// Out-of-bounds index [~0].
- EXPECT_EQ(
- dif_clkmgr_gateable_clock_set_enabled(
- &clkmgr_, std::numeric_limits<dif_clkmgr_gateable_clock_t>::max(),
- kDifClkmgrToggleEnabled),
- kDifClkmgrBadArg);
+ EXPECT_EQ(dif_clkmgr_gateable_clock_set_enabled(
+ &clkmgr_, params_,
+ std::numeric_limits<dif_clkmgr_gateable_clock_t>::max(),
+ kDifToggleEnabled),
+ kDifBadArg);
// Out-of-bounds index [last+1].
- EXPECT_EQ(
- dif_clkmgr_gateable_clock_set_enabled(
- &clkmgr_, CLKMGR_CLK_ENABLES_LAST_BIT + 1, kDifClkmgrToggleDisabled),
- kDifClkmgrBadArg);
+ EXPECT_EQ(dif_clkmgr_gateable_clock_set_enabled(
+ &clkmgr_, params_, CLKMGR_CLK_ENABLES_LAST_BIT + 1,
+ kDifToggleDisabled),
+ kDifBadArg);
}
TEST_F(GateableClockTest, GetEnabled) {
@@ -121,10 +124,10 @@
bool enabled = false;
EXPECT_READ32(CLKMGR_CLK_ENABLES_REG_OFFSET,
{{CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT, true}});
- EXPECT_EQ(
- dif_clkmgr_gateable_clock_get_enabled(
- &clkmgr_, CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT, &enabled),
- kDifClkmgrOk);
+ EXPECT_EQ(dif_clkmgr_gateable_clock_get_enabled(
+ &clkmgr_, params_, CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT,
+ &enabled),
+ kDifOk);
EXPECT_TRUE(enabled);
}
@@ -134,8 +137,9 @@
EXPECT_READ32(CLKMGR_CLK_ENABLES_REG_OFFSET,
{{CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT, false}});
EXPECT_EQ(dif_clkmgr_gateable_clock_get_enabled(
- &clkmgr_, CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT, &enabled),
- kDifClkmgrOk);
+ &clkmgr_, params_, CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
+ &enabled),
+ kDifOk);
EXPECT_FALSE(enabled);
}
}
@@ -145,25 +149,27 @@
// Null handle.
EXPECT_EQ(dif_clkmgr_gateable_clock_get_enabled(
- nullptr, CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT, &enabled),
- kDifClkmgrBadArg);
+ nullptr, params_, CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT,
+ &enabled),
+ kDifBadArg);
// Null result.
EXPECT_EQ(dif_clkmgr_gateable_clock_get_enabled(
- &clkmgr_, CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT, nullptr),
- kDifClkmgrBadArg);
+ &clkmgr_, params_, CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT,
+ nullptr),
+ kDifBadArg);
// Out-of-bounds index [~0].
EXPECT_EQ(
dif_clkmgr_gateable_clock_get_enabled(
- &clkmgr_, std::numeric_limits<dif_clkmgr_gateable_clock_t>::max(),
- &enabled),
- kDifClkmgrBadArg);
+ &clkmgr_, params_,
+ std::numeric_limits<dif_clkmgr_gateable_clock_t>::max(), &enabled),
+ kDifBadArg);
// Out-of-bounds index [last+1].
EXPECT_EQ(dif_clkmgr_gateable_clock_get_enabled(
- &clkmgr_, CLKMGR_CLK_ENABLES_LAST_BIT + 1, &enabled),
- kDifClkmgrBadArg);
+ &clkmgr_, params_, CLKMGR_CLK_ENABLES_LAST_BIT + 1, &enabled),
+ kDifBadArg);
}
class HintableClockTest : public ClkMgrTest {};
@@ -173,37 +179,38 @@
EXPECT_MASK32(CLKMGR_CLK_HINTS_REG_OFFSET,
{{CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT, 0x1, false}});
EXPECT_EQ(dif_clkmgr_hintable_clock_set_hint(
- &clkmgr_, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT,
- kDifClkmgrToggleDisabled),
- kDifClkmgrOk);
+ &clkmgr_, params_, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT,
+ kDifToggleDisabled),
+ kDifOk);
// Enable hint.
EXPECT_MASK32(CLKMGR_CLK_HINTS_REG_OFFSET,
{{CLKMGR_CLK_HINTS_LAST_BIT, 0x1, true}});
- EXPECT_EQ(dif_clkmgr_hintable_clock_set_hint(
- &clkmgr_, CLKMGR_CLK_HINTS_LAST_BIT, kDifClkmgrToggleEnabled),
- kDifClkmgrOk);
+ EXPECT_EQ(
+ dif_clkmgr_hintable_clock_set_hint(
+ &clkmgr_, params_, CLKMGR_CLK_HINTS_LAST_BIT, kDifToggleEnabled),
+ kDifOk);
}
TEST_F(HintableClockTest, SetHintError) {
// Null handle.
EXPECT_EQ(dif_clkmgr_hintable_clock_set_hint(
- nullptr, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT,
- kDifClkmgrToggleEnabled),
- kDifClkmgrBadArg);
+ nullptr, params_, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT,
+ kDifToggleEnabled),
+ kDifBadArg);
// Out-of-bounds index [~0].
- EXPECT_EQ(
- dif_clkmgr_hintable_clock_set_hint(
- &clkmgr_, std::numeric_limits<dif_clkmgr_hintable_clock_t>::max(),
- kDifClkmgrToggleEnabled),
- kDifClkmgrBadArg);
+ EXPECT_EQ(dif_clkmgr_hintable_clock_set_hint(
+ &clkmgr_, params_,
+ std::numeric_limits<dif_clkmgr_hintable_clock_t>::max(),
+ kDifToggleEnabled),
+ kDifBadArg);
// Out-of-bounds index [last+1].
EXPECT_EQ(
dif_clkmgr_hintable_clock_set_hint(
- &clkmgr_, CLKMGR_CLK_HINTS_LAST_BIT + 1, kDifClkmgrToggleDisabled),
- kDifClkmgrBadArg);
+ &clkmgr_, params_, CLKMGR_CLK_HINTS_LAST_BIT + 1, kDifToggleDisabled),
+ kDifBadArg);
}
TEST_F(HintableClockTest, GetHint) {
@@ -213,8 +220,9 @@
EXPECT_READ32(CLKMGR_CLK_HINTS_REG_OFFSET,
{{CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT, true}});
EXPECT_EQ(dif_clkmgr_hintable_clock_get_hint(
- &clkmgr_, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT, &enabled),
- kDifClkmgrOk);
+ &clkmgr_, params_, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT,
+ &enabled),
+ kDifOk);
EXPECT_TRUE(enabled);
}
@@ -224,8 +232,9 @@
EXPECT_READ32(CLKMGR_CLK_HINTS_REG_OFFSET,
{{CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT, false}});
EXPECT_EQ(dif_clkmgr_hintable_clock_get_hint(
- &clkmgr_, CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT, &enabled),
- kDifClkmgrOk);
+ &clkmgr_, params_, CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT,
+ &enabled),
+ kDifOk);
EXPECT_FALSE(enabled);
}
}
@@ -234,26 +243,28 @@
bool enabled = false;
// Null handle.
- EXPECT_EQ(dif_clkmgr_hintable_clock_get_hint(
- nullptr, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT, &enabled),
- kDifClkmgrBadArg);
+ EXPECT_EQ(
+ dif_clkmgr_hintable_clock_get_hint(
+ nullptr, params_, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT, &enabled),
+ kDifBadArg);
// Null result.
- EXPECT_EQ(dif_clkmgr_hintable_clock_get_hint(
- &clkmgr_, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT, nullptr),
- kDifClkmgrBadArg);
+ EXPECT_EQ(
+ dif_clkmgr_hintable_clock_get_hint(
+ &clkmgr_, params_, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT, nullptr),
+ kDifBadArg);
// Out-of-bounds index [~0].
EXPECT_EQ(
dif_clkmgr_hintable_clock_get_hint(
- &clkmgr_, std::numeric_limits<dif_clkmgr_hintable_clock_t>::max(),
- &enabled),
- kDifClkmgrBadArg);
+ &clkmgr_, params_,
+ std::numeric_limits<dif_clkmgr_hintable_clock_t>::max(), &enabled),
+ kDifBadArg);
// Out-of-bounds index [last+1].
EXPECT_EQ(dif_clkmgr_hintable_clock_get_hint(
- &clkmgr_, CLKMGR_CLK_HINTS_LAST_BIT + 1, &enabled),
- kDifClkmgrBadArg);
+ &clkmgr_, params_, CLKMGR_CLK_HINTS_LAST_BIT + 1, &enabled),
+ kDifBadArg);
}
TEST_F(HintableClockTest, GetEnabled) {
@@ -262,10 +273,10 @@
bool enabled = true;
EXPECT_READ32(CLKMGR_CLK_HINTS_STATUS_REG_OFFSET,
{{CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_AES_VAL_BIT, false}});
- EXPECT_EQ(
- dif_clkmgr_hintable_clock_get_enabled(
- &clkmgr_, CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_AES_VAL_BIT, &enabled),
- kDifClkmgrOk);
+ EXPECT_EQ(dif_clkmgr_hintable_clock_get_enabled(
+ &clkmgr_, params_,
+ CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_AES_VAL_BIT, &enabled),
+ kDifOk);
EXPECT_FALSE(enabled);
}
@@ -274,10 +285,10 @@
bool enabled = false;
EXPECT_READ32(CLKMGR_CLK_HINTS_STATUS_REG_OFFSET,
{{CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT, true}});
- EXPECT_EQ(
- dif_clkmgr_hintable_clock_get_enabled(
- &clkmgr_, CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT, &enabled),
- kDifClkmgrOk);
+ EXPECT_EQ(dif_clkmgr_hintable_clock_get_enabled(
+ &clkmgr_, params_,
+ CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT, &enabled),
+ kDifOk);
EXPECT_TRUE(enabled);
}
}
@@ -286,28 +297,29 @@
bool enabled = false;
// Null handle.
- EXPECT_EQ(
- dif_clkmgr_hintable_clock_get_enabled(
- nullptr, CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_AES_VAL_BIT, &enabled),
- kDifClkmgrBadArg);
+ EXPECT_EQ(dif_clkmgr_hintable_clock_get_enabled(
+ nullptr, params_, CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_AES_VAL_BIT,
+ &enabled),
+ kDifBadArg);
// Null result.
- EXPECT_EQ(
- dif_clkmgr_hintable_clock_get_enabled(
- &clkmgr_, CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_AES_VAL_BIT, nullptr),
- kDifClkmgrBadArg);
+ EXPECT_EQ(dif_clkmgr_hintable_clock_get_enabled(
+ &clkmgr_, params_, CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_AES_VAL_BIT,
+ nullptr),
+ kDifBadArg);
// Out-of-bounds index [~0].
EXPECT_EQ(
dif_clkmgr_hintable_clock_get_enabled(
- &clkmgr_, std::numeric_limits<dif_clkmgr_hintable_clock_t>::max(),
- &enabled),
- kDifClkmgrBadArg);
+ &clkmgr_, params_,
+ std::numeric_limits<dif_clkmgr_hintable_clock_t>::max(), &enabled),
+ kDifBadArg);
// Out-of-bounds index [last+1].
- EXPECT_EQ(dif_clkmgr_hintable_clock_get_enabled(
- &clkmgr_, CLKMGR_CLK_HINTS_STATUS_LAST_BIT + 1, &enabled),
- kDifClkmgrBadArg);
+ EXPECT_EQ(
+ dif_clkmgr_hintable_clock_get_enabled(
+ &clkmgr_, params_, CLKMGR_CLK_HINTS_STATUS_LAST_BIT + 1, &enabled),
+ kDifBadArg);
}
} // namespace
diff --git a/sw/device/lib/dif/meson.build b/sw/device/lib/dif/meson.build
index 8dccd72..2f86b4e 100644
--- a/sw/device/lib/dif/meson.build
+++ b/sw/device/lib/dif/meson.build
@@ -14,6 +14,7 @@
],
dependencies: [
sw_lib_mmio,
+ sw_lib_dif_autogen_clkmgr,
],
)
)
@@ -21,9 +22,10 @@
test('dif_clkmgr_unittest', executable(
'dif_clkmgr_unittest',
sources: [
- hw_ip_clkmgr_reg_h,
+ 'autogen/dif_clkmgr_autogen_unittest.cc',
meson.source_root() / 'sw/device/lib/dif/dif_clkmgr.c',
- 'dif_clkmgr_unittest.cc',
+ meson.source_root() / 'sw/device/lib/dif/autogen/dif_clkmgr_autogen.c',
+ hw_ip_clkmgr_reg_h,
],
dependencies: [
sw_vendor_gtest,
diff --git a/sw/device/sca/lib/sca.c b/sw/device/sca/lib/sca.c
index e894f17..4a431b9 100644
--- a/sw/device/sca/lib/sca.c
+++ b/sw/device/sca/lib/sca.c
@@ -169,39 +169,40 @@
// Disable HMAC, KMAC, OTBN and USB clocks through CLKMGR DIF.
const dif_clkmgr_params_t clkmgr_params = {
- .base_addr = mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR),
.last_gateable_clock = CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
.last_hintable_clock = CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT};
dif_clkmgr_t clkmgr;
- IGNORE_RESULT(dif_clkmgr_init(clkmgr_params, &clkmgr));
+ IGNORE_RESULT(
+ dif_clkmgr_init(mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR),
+ clkmgr_params, &clkmgr));
if (disable & kScaPeripheralAes) {
IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
- &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT,
- kDifClkmgrToggleDisabled));
+ &clkmgr, clkmgr_params, CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT,
+ kDifToggleDisabled));
}
if (disable & kScaPeripheralHmac) {
IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
- &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT,
- kDifClkmgrToggleDisabled));
+ &clkmgr, clkmgr_params, CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT,
+ kDifToggleDisabled));
}
if (disable & kScaPeripheralKmac) {
IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
- &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_KMAC_HINT_BIT,
- kDifClkmgrToggleDisabled));
+ &clkmgr, clkmgr_params, CLKMGR_CLK_HINTS_CLK_MAIN_KMAC_HINT_BIT,
+ kDifToggleDisabled));
}
if (disable & kScaPeripheralOtbn) {
IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
- &clkmgr, CLKMGR_CLK_HINTS_CLK_IO_DIV4_OTBN_HINT_BIT,
- kDifClkmgrToggleDisabled));
+ &clkmgr, clkmgr_params, CLKMGR_CLK_HINTS_CLK_IO_DIV4_OTBN_HINT_BIT,
+ kDifToggleDisabled));
IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
- &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT,
- kDifClkmgrToggleDisabled));
+ &clkmgr, clkmgr_params, CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT,
+ kDifToggleDisabled));
}
if (disable & kScaPeripheralUsb) {
IGNORE_RESULT(dif_clkmgr_gateable_clock_set_enabled(
- &clkmgr, CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
- kDifClkmgrToggleDisabled));
+ &clkmgr, clkmgr_params, CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
+ kDifToggleDisabled));
}
}
diff --git a/sw/device/tests/clkmgr_smoketest.c b/sw/device/tests/clkmgr_smoketest.c
index c7ce522..4f76a2b 100644
--- a/sw/device/tests/clkmgr_smoketest.c
+++ b/sw/device/tests/clkmgr_smoketest.c
@@ -3,6 +3,7 @@
// SPDX-License-Identifier: Apache-2.0
#include "sw/device/lib/base/memory.h"
+#include "sw/device/lib/dif/dif_base.h"
#include "sw/device/lib/dif/dif_clkmgr.h"
#include "sw/device/lib/testing/check.h"
#include "sw/device/lib/testing/test_framework/test_main.h"
@@ -15,7 +16,8 @@
* Test that all 'gateable' clocks, directly controlled by software,
* can be enabled and disabled.
*/
-static void test_gateable_clocks(const dif_clkmgr_t *clkmgr) {
+static void test_gateable_clocks(const dif_clkmgr_t *clkmgr,
+ dif_clkmgr_params_t params) {
const dif_clkmgr_gateable_clock_t clocks[] = {
kTopEarlgreyGateableClocksIoDiv4Peri,
kTopEarlgreyGateableClocksUsbPeri,
@@ -28,18 +30,17 @@
// disabled depending on reset behavior - either is fine for the purposes of
// this test.
bool enabled;
- CHECK(dif_clkmgr_gateable_clock_get_enabled(clkmgr, clock, &enabled) ==
- kDifClkmgrOk);
+ CHECK_DIF_OK(
+ dif_clkmgr_gateable_clock_get_enabled(clkmgr, params, clock, &enabled));
// Toggle the enable twice so that it ends up in its original state.
for (int j = 0; j < 2; ++j) {
bool expected = !enabled;
- CHECK(dif_clkmgr_gateable_clock_set_enabled(
- clkmgr, clock,
- expected ? kDifClkmgrToggleEnabled
- : kDifClkmgrToggleDisabled) == kDifClkmgrOk);
- CHECK(dif_clkmgr_gateable_clock_get_enabled(clkmgr, clock, &enabled) ==
- kDifClkmgrOk);
+ CHECK_DIF_OK(dif_clkmgr_gateable_clock_set_enabled(
+ clkmgr, params, clock,
+ expected ? kDifToggleEnabled : kDifToggleDisabled));
+ CHECK_DIF_OK(dif_clkmgr_gateable_clock_get_enabled(clkmgr, params, clock,
+ &enabled));
CHECK(enabled == expected);
}
}
@@ -49,7 +50,8 @@
* Test that all 'hintable' clocks, indirectly controlled by software,
* can have their hint toggled and status checked.
*/
-void test_hintable_clocks(const dif_clkmgr_t *clkmgr) {
+void test_hintable_clocks(const dif_clkmgr_t *clkmgr,
+ dif_clkmgr_params_t params) {
const dif_clkmgr_hintable_clock_t clocks[] = {
kTopEarlgreyHintableClocksMainAes,
kTopEarlgreyHintableClocksMainHmac,
@@ -64,25 +66,24 @@
// enabled or disabled depending on reset behavior - either is fine for the
// purposes of this test.
bool enabled;
- CHECK(dif_clkmgr_hintable_clock_get_hint(clkmgr, clock, &enabled) ==
- kDifClkmgrOk);
+ CHECK_DIF_OK(
+ dif_clkmgr_hintable_clock_get_hint(clkmgr, params, clock, &enabled));
// Toggle the hint twice so that it ends up in its original state.
for (int j = 0; j < 2; ++j) {
bool expected = !enabled;
- CHECK(dif_clkmgr_hintable_clock_set_hint(
- clkmgr, clock,
- expected ? kDifClkmgrToggleEnabled
- : kDifClkmgrToggleDisabled) == kDifClkmgrOk);
- CHECK(dif_clkmgr_hintable_clock_get_hint(clkmgr, clock, &enabled) ==
- kDifClkmgrOk);
+ CHECK_DIF_OK(dif_clkmgr_hintable_clock_set_hint(
+ clkmgr, params, clock,
+ expected ? kDifToggleEnabled : kDifToggleDisabled));
+ CHECK_DIF_OK(
+ dif_clkmgr_hintable_clock_get_hint(clkmgr, params, clock, &enabled));
CHECK(enabled == expected);
// If the clock hint is enabled then the clock should always be enabled.
if (enabled) {
bool status = false;
- CHECK(dif_clkmgr_hintable_clock_get_enabled(clkmgr, clock, &status) ==
- kDifClkmgrOk);
+ CHECK_DIF_OK(dif_clkmgr_hintable_clock_get_enabled(clkmgr, params,
+ clock, &status));
CHECK(status, "clock %u hint is enabled but status is disabled", clock);
}
}
@@ -91,15 +92,16 @@
bool test_main() {
const dif_clkmgr_params_t params = {
- .base_addr = mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR),
.last_gateable_clock = kTopEarlgreyGateableClocksLast,
.last_hintable_clock = kTopEarlgreyHintableClocksLast,
};
dif_clkmgr_t clkmgr;
- CHECK(dif_clkmgr_init(params, &clkmgr) == kDifClkmgrOk);
- test_gateable_clocks(&clkmgr);
- test_hintable_clocks(&clkmgr);
+ CHECK_DIF_OK(
+ dif_clkmgr_init(mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR),
+ params, &clkmgr));
+ test_gateable_clocks(&clkmgr, params);
+ test_hintable_clocks(&clkmgr, params);
return true;
}
