[top] revert ast pok bypass
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
index 330a808..8f69ab1 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
@@ -815,9 +815,12 @@
//////////////////////////////////
-
assign ast_base_pwr.main_pok = ast_pwst.main_pok;
+ logic [rstmgr_pkg::PowerDomains-1:0] por_n;
+ assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok};
+
+
logic [ast_pkg::UsbCalibWidth-1:0] usb_io_pu_cal;
// external clock comes in at a fixed position
@@ -1067,9 +1070,6 @@
//////////////////////
// Top-level design //
//////////////////////
-
- logic [rstmgr_pkg::PowerDomains-1:0] por_n;
- assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok};
top_earlgrey #(
.PinmuxAonTargetCfg(PinmuxTargetCfg)
) top_earlgrey (
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
index fbfaaeb..0bf596a 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
@@ -778,12 +778,15 @@
//////////////////////////////////
+ assign ast_base_pwr.main_pok = ast_pwst.main_pok;
+
+ logic [rstmgr_pkg::PowerDomains-1:0] por_n;
+ assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok};
+
// TODO: Hook this up when FPGA pads are updated
assign ext_clk = '0;
assign pad2ast = '0;
- assign ast_base_pwr.main_pok = base_ast_pwr.main_pd_n;
-
logic clk_main, clk_usb_48mhz, clk_aon, rst_n, srst_n;
clkgen_xil7series # (
.AddClkBuf(0)
@@ -1001,7 +1004,7 @@
.SramCtrlMainInstrExec(1),
.PinmuxAonTargetCfg(PinmuxTargetCfg)
) top_earlgrey (
- .por_n_i ( {rst_n, rst_n} ),
+ .por_n_i ( por_n ),
.clk_main_i ( ast_base_clks.clk_sys ),
.clk_io_i ( ast_base_clks.clk_io ),
.clk_usb_i ( ast_base_clks.clk_usb ),
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index f33a013..92b3faa 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -601,10 +601,13 @@
ast = ast[0]
%>\
-% if target["name"] == "asic":
-
assign ast_base_pwr.main_pok = ast_pwst.main_pok;
+ logic [rstmgr_pkg::PowerDomains-1:0] por_n;
+ assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok};
+
+% if target["name"] == "asic":
+
logic [ast_pkg::UsbCalibWidth-1:0] usb_io_pu_cal;
// external clock comes in at a fixed position
@@ -635,8 +638,6 @@
assign ext_clk = '0;
assign pad2ast = '0;
- assign ast_base_pwr.main_pok = base_ast_pwr.main_pd_n;
-
logic clk_main, clk_usb_48mhz, clk_aon, rst_n, srst_n;
clkgen_xil7series # (
.AddClkBuf(0)
@@ -906,9 +907,6 @@
//////////////////////
// Top-level design //
//////////////////////
-
- logic [rstmgr_pkg::PowerDomains-1:0] por_n;
- assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok};
top_${top["name"]} #(
.PinmuxAonTargetCfg(PinmuxTargetCfg)
) top_${top["name"]} (
@@ -1093,7 +1091,7 @@
.SramCtrlMainInstrExec(1),
.PinmuxAonTargetCfg(PinmuxTargetCfg)
) top_${top["name"]} (
- .por_n_i ( {rst_n, rst_n} ),
+ .por_n_i ( por_n ),
.clk_main_i ( ast_base_clks.clk_sys ),
.clk_io_i ( ast_base_clks.clk_io ),
.clk_usb_i ( ast_base_clks.clk_usb ),
