[topgen] Lint cleanup only
- Kept most of the lint cleanups suggested by util/lintpy.py.
- No functional change.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/util/topgen.py b/util/topgen.py
index 11bea96..0fcab0c 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -18,12 +18,11 @@
from typing import Dict, List, Optional, Tuple
import hjson
+import tlgen
from ipgen import (IpBlockRenderer, IpConfig, IpDescriptionOnlyRenderer,
IpTemplate, TemplateRenderError)
from mako import exceptions
from mako.template import Template
-
-import tlgen
from reggen import access, gen_rtl, window
from reggen.inter_signal import InterSignal
from reggen.ip_block import IpBlock
@@ -33,12 +32,12 @@
from topgen import lib as lib
from topgen import merge_top, search_ips, validate_top
from topgen.c_test import TopGenCTest
+from topgen.clocks import Clocks
from topgen.gen_dv import gen_dv
from topgen.gen_top_docs import gen_top_docs
-from topgen.top import Top
-from topgen.clocks import Clocks
-from topgen.merge import extract_clocks, connect_clocks, create_alert_lpgs
+from topgen.merge import connect_clocks, create_alert_lpgs, extract_clocks
from topgen.resets import Resets
+from topgen.top import Top
# Common header for generated files
warnhdr = '''//
@@ -148,13 +147,13 @@
use_decimal=True,
object_pairs_hook=OrderedDict)
- r_inter_signal_list = check_list(xbar_ipobj.get('inter_signal_list', []),
- 'inter_signal_list field')
+ r_inter_signal_list = check_list(
+ xbar_ipobj.get('inter_signal_list', []),
+ 'inter_signal_list field')
obj['inter_signal_list'] = [
- InterSignal.from_raw('entry {} of the inter_signal_list field'
- .format(idx + 1),
- entry)
- for idx, entry in enumerate(r_inter_signal_list)
+ InterSignal.from_raw(
+ 'entry {} of the inter_signal_list field'.format(idx + 1),
+ entry) for idx, entry in enumerate(r_inter_signal_list)
]
@@ -220,8 +219,8 @@
# Count number of interrupts
# Interrupt source 0 is tied to 0 to conform RISC-V PLIC spec.
# So, total number of interrupts are the number of entries in the list + 1
- params['src'] = sum([x["width"] if "width" in x else 1
- for x in top["interrupt"]]) + 1
+ params['src'] = sum(
+ [x["width"] if "width" in x else 1 for x in top["interrupt"]]) + 1
# Target and priority: Currently fixed
params['target'] = int(top["num_cores"], 0) if "num_cores" in top else 1
@@ -328,8 +327,7 @@
n_dio_pads=n_dio_pads,
attr_dw=attr_dw,
n_wkup_detect=num_wkup_detect,
- wkup_cnt_width=wkup_cnt_width
- )
+ wkup_cnt_width=wkup_cnt_width)
except: # noqa: E722
log.error(exceptions.text_error_template().render())
log.info("PINMUX HJSON: %s" % out)
@@ -414,9 +412,8 @@
if n_rstreqs < 1:
n_rstreqs = 1
- log.warning(
- "The design has no reset request sources. "
- "Reset requests are not supported.")
+ log.warning("The design has no reset request sources. "
+ "Reset requests are not supported.")
# Define target path
rtl_path = out_path / 'ip/pwrmgr/rtl/autogen'
@@ -541,10 +538,10 @@
# Read template files from ip directory.
tpls = []
outputs = []
- names = ['flash_ctrl.hjson',
- 'flash_ctrl.sv',
- 'flash_ctrl_pkg.sv',
- 'flash_ctrl_region_cfg.sv']
+ names = [
+ 'flash_ctrl.hjson', 'flash_ctrl.sv', 'flash_ctrl_pkg.sv',
+ 'flash_ctrl_region_cfg.sv'
+ ]
for x in names:
tpls.append(tpl_path / Path(x + ".tpl"))
@@ -554,7 +551,9 @@
outputs.append(rtl_path / Path(x))
# Parameters needed for generation
- flash_mems = [module for module in topcfg['module'] if module['type'] == 'flash_ctrl']
+ flash_mems = [
+ module for module in topcfg['module'] if module['type'] == 'flash_ctrl'
+ ]
if len(flash_mems) > 1:
log.error("This design does not currently support multiple flashes")
return
@@ -603,13 +602,12 @@
ip, hjson_path, genrtl_dir))
# Generate reg files
- gen_rtl.gen_rtl(IpBlock.from_path(str(hjson_path), []), str(genrtl_dir))
+ gen_rtl.gen_rtl(IpBlock.from_path(str(hjson_path), []),
+ str(genrtl_dir))
-def generate_top_ral(top: Dict[str, object],
- name_to_block: Dict[str, IpBlock],
- dv_base_names: List[str],
- out_path: str):
+def generate_top_ral(top: Dict[str, object], name_to_block: Dict[str, IpBlock],
+ dv_base_names: List[str], out_path: str):
# construct top ral block
regwidth = int(top['datawidth'])
@@ -692,8 +690,7 @@
item["data_intg_passthru"].lower() == "true")
size_in_bytes = int(item['size'], 0)
num_regs = size_in_bytes // addrsep
- swaccess = access.SWAccess('top-level memory',
- item.get('swaccess', 'rw'))
+ swaccess = access.SWAccess('top-level memory', item.get('swaccess', 'rw'))
return window.Window(name=item['name'],
desc='(generated from top-level)',
@@ -720,8 +717,7 @@
# and therefore not part of "hw/ip"
top_only_dict = {
module['type']: lib.is_reggen_only(module)
- for module in topcfg['module']
- if lib.is_top_reggen(module)
+ for module in topcfg['module'] if lib.is_top_reggen(module)
}
log.info("Filtered dict is {}".format(top_only_dict))
@@ -763,9 +759,11 @@
desc_file_relpath = 'data/autogen'
if ip == 'clkmgr' or (pass_idx > 0):
- ip_hjson = Path(out_path) / ip_relpath / ip / desc_file_relpath / f"{ip}.hjson"
+ ip_hjson = (Path(out_path) / ip_relpath / ip / desc_file_relpath /
+ f"{ip}.hjson")
else:
- ip_hjson = hjson_dir.parent / ip_relpath / ip / desc_file_relpath / f"{ip}.hjson"
+ ip_hjson = (hjson_dir.parent / ip_relpath / ip /
+ desc_file_relpath / f"{ip}.hjson")
ips.append(ip_hjson)
for ip, reggen_only in top_only_dict.items():
@@ -800,8 +798,7 @@
log.info(
"To-be-auto-generated Hjson %s does not yet exist. "
"Falling back to the default configuration of template "
- "%s for initial validation." %
- (ip_desc_file, ip_name))
+ "%s for initial validation." % (ip_desc_file, ip_name))
tpl_path = SRCTREE_TOP / 'hw/ip_templates' / ip_name
ip_template = IpTemplate.from_template_path(tpl_path)
@@ -925,8 +922,7 @@
This applies only to ip's with the `reggen_only` attribute.
If an hjson is located both in the conventional path and the alternate
path, the alternate path has priority.
- '''
- )
+ ''')
parser.add_argument('--verbose', '-v', action='store_true', help="Verbose")
# Generator options: 'no' series. cannot combined with 'only' series
@@ -968,10 +964,11 @@
default=False,
action='store_true',
help="If set, the tool generates top level RAL model for DV")
- parser.add_argument('--dv-base-names',
- nargs="+",
- help='Names or prefix for the DV register classes from which '
- 'the register models are derived.')
+ parser.add_argument(
+ '--dv-base-names',
+ nargs="+",
+ help='Names or prefix for the DV register classes from which '
+ 'the register models are derived.')
# Generator options for compile time random netlist constants
parser.add_argument(
'--rnd_cnst_seed',
@@ -998,8 +995,8 @@
raise SystemExit(sys.exc_info()[1])
# Don't print warnings when querying the list of blocks.
- log_level = (log.ERROR if args.get_blocks else
- log.DEBUG if args.verbose else None)
+ log_level = (log.ERROR
+ if args.get_blocks else log.DEBUG if args.verbose else None)
log.basicConfig(format="%(levelname)s: %(message)s", level=log_level)
@@ -1116,7 +1113,9 @@
hjson.dumps(completecfg, for_json=True))
if not args.no_top or args.top_only:
- def render_template(template_path: str, rendered_path: Path, **other_info):
+
+ def render_template(template_path: str, rendered_path: Path,
+ **other_info):
template_contents = generate_top(completecfg, name_to_block,
str(template_path), **other_info)
@@ -1140,7 +1139,8 @@
# Multiple chip-levels (ASIC, FPGA, Verilator, etc)
for target in topcfg['targets']:
render_template(TOPGEN_TEMPLATE_PATH / "chiplevel.sv.tpl",
- out_path / f"rtl/autogen/chip_{topname}_{target['name']}.sv",
+ out_path /
+ f"rtl/autogen/chip_{topname}_{target['name']}.sv",
gencmd=gencmd,
target=target)
@@ -1156,7 +1156,8 @@
# compile-time random netlist constants
render_template(TOPGEN_TEMPLATE_PATH / "toplevel_rnd_cnst_pkg.sv.tpl",
- out_path / f"rtl/autogen/top_{topname}_rnd_cnst_pkg.sv",
+ out_path /
+ f"rtl/autogen/top_{topname}_rnd_cnst_pkg.sv",
gencmd=gencmd)
# C Header + C File + Clang-format file
