[dv/rstmgr] Simplify reset checking
Minor coverage tuning for reset_req mubi.
Signed-off-by: Guillermo Maturana <maturana@google.com>
diff --git a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
index 060a811..286429f 100644
--- a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
+++ b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
@@ -11,6 +11,8 @@
`uvm_object_utils(rstmgr_base_vseq)
+ `uvm_object_new
+
// Set clock frequencies per spec, except the aon is 200kHZ, which is
// too slow and could slow testing down for no good reason.
localparam int AON_FREQ_MHZ = 3;
@@ -41,14 +43,8 @@
} reset_e;
typedef struct {
- int code;
- logic enable;
- logic update;
- } reset_expectations_t;
-
- typedef struct {
string description;
- reset_expectations_t expects;
+ int code;
} reset_test_info_t;
rand reset_e which_reset;
@@ -97,55 +93,37 @@
reset_test_info_t reset_test_infos[reset_e] = '{
ResetPOR: '{
description: "POR reset",
- expects: '{
- code: 1,
- enable: 1'b0,
- update: 1'b0
- }
+ code: 1
},
ResetScan: '{
description: "scan reset",
- expects: '{
- code: 1,
- enable: 1'b0,
- update: 1'b0
- }
+ code: 1
},
ResetLowPower: '{
description: "low power reset",
- expects: '{
- code: 2,
- enable: 1'b1,
- update: 1'b1
- }
+ code: 2
},
ResetNdm: '{
description: "ndm reset",
- expects: '{
- code: 4,
- enable: 1'b1,
- update: 1'b1
- }
+ code: 4
},
ResetSw: '{
description: "software reset",
- expects: '{
- code: 8,
- enable: 1'b0,
- update: 1'b1
- }
+ code: 8
},
ResetHw: '{
description: "hardware reset",
- expects: '{
- code: 16,
- enable: 1'b0,
- update: 1'b1
- }
+ code: 16
}
};
- `uvm_object_new
+ function bit aon_reset(reset_e reset);
+ return reset inside {ResetPOR, ResetScan};
+ endfunction
+
+ function bit clear_capture_enable(reset_e reset);
+ return !(reset inside {ResetLowPower, ResetNdm});
+ endfunction
function void post_randomize();
scanmode = get_rand_mubi4_val(scanmode_on_weight, 4, 4);
@@ -306,7 +284,7 @@
virtual protected task clear_alert_and_cpu_info();
set_alert_and_cpu_info_for_capture('0, '0);
- send_sw_reset();
+ send_sw_reset(MuBi4True);
check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(0));
endtask
@@ -400,12 +378,14 @@
endtask
// Requests a sw reset. It is cleared by hardware once the reset is taken.
- virtual protected task send_sw_reset();
- `uvm_info(`gfn, "Sending sw reset", UVM_LOW)
- csr_wr(.ptr(ral.reset_req), .value(prim_mubi_pkg::MuBi4True));
- reset_start(pwrmgr_pkg::HwReq);
- cfg.io_div4_clk_rst_vif.wait_clks(non_ndm_reset_cycles);
- reset_done();
+ virtual protected task send_sw_reset(mubi4_t value);
+ csr_wr(.ptr(ral.reset_req), .value(value));
+ if (value == prim_mubi_pkg::MuBi4True) begin
+ `uvm_info(`gfn, "Sending sw reset", UVM_LOW)
+ reset_start(pwrmgr_pkg::HwReq);
+ cfg.io_div4_clk_rst_vif.wait_clks(non_ndm_reset_cycles);
+ reset_done();
+ end
endtask
virtual task dut_init(string reset_kind = "HARD");
diff --git a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv
index 3964fa4..6be67ac 100644
--- a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv
+++ b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv
@@ -2,25 +2,32 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-// Tests the reset_info CSR settings for random resets.
-// Notice as far as rstmgr once POR or scan reset are asserted, they have
-// identical side-effects for rstmgr.
+// Tests the reset_info CSR settings, and alert and cpu dump capture for random
+// resets.
+//
+// Notice that for rstmgr both POR and scan reset have identical side-effects.
//
// Each run releases rst_cpu_n a few cycles after a scan reset. This requires
// the responder to be disabled from automatically deactivating rst_cpu_n after
// rst_sys_src_n goes inactive.
//
-// It is simpler to manipulate the responder once running so we cause a scan
-// reset after disabling it, and before the other resets. This tests that resets
-// other than scan don't update the reset_info CSR, and don't capture cpu or
-// alert dumps.
+// It is simpler to manipulate the responder once running so we cause another
+// aon reset after disabling it, and before the other resets. This tests that,
+// prior to rst_cpu_n, non-aon resets don't update the reset_info CSR, and don't
+// capture cpu or alert dumps.
class rstmgr_reset_vseq extends rstmgr_base_vseq;
`uvm_object_utils(rstmgr_reset_vseq)
`uvm_object_new
- rand logic enable_alert_info;
- rand logic enable_cpu_info;
+ constraint num_trans_c {num_trans inside {[40 : 60]};}
+
+ constraint which_reset_c {which_reset != 0;}
+
+ // VCS seems to have non-uniform distributions for this variable.
+ rand logic alert_enable;
+
+ rand logic cpu_enable;
rand int wait_for_release_response_update_cycles;
constraint wait_for_release_response_update_cycles_c {
@@ -36,6 +43,13 @@
rand reset_e start_reset;
constraint start_reset_c {start_reset inside {ResetPOR, ResetScan};}
+ mubi4_t sw_reset_csr;
+
+ function void post_randomize();
+ if (which_reset == ResetSw) sw_reset_csr = MuBi4True;
+ else sw_reset_csr = get_rand_mubi4_val(0, 2, 4);
+ endfunction
+
local task update_cpu_to_sys_rst_release_response(bit enable);
enable_cpu_to_sys_rst_release_response = enable;
`uvm_info(`gfn, $sformatf("%0sabling sys_rst_responder", enable ? "En" : "Dis"), UVM_MEDIUM)
@@ -57,6 +71,8 @@
int expected_reset_info_code;
logic expected_alert_enable;
logic expected_cpu_enable;
+ alert_crashdump_t expected_alert_dump = '0;
+ cpu_crash_dump_t expected_cpu_dump = '0;
alert_crashdump_t prev_alert_dump = '0;
cpu_crash_dump_t prev_cpu_dump = '0;
int trans_before_enabling_cpu_rst_response;
@@ -79,54 +95,78 @@
), UVM_MEDIUM)
// Clear reset_info register, and enable cpu and alert info capture.
- set_alert_info_for_capture(alert_dump, enable_alert_info);
- set_cpu_info_for_capture(cpu_dump, enable_cpu_info);
+ set_alert_info_for_capture(alert_dump, alert_enable);
+ set_cpu_info_for_capture(cpu_dump, cpu_enable);
csr_wr(.ptr(ral.reset_info), .value('1));
// We need to start with an AON reset to process non-capturing resets.
if (start_reset == ResetPOR) por_reset();
else if (start_reset == ResetScan) send_scan_reset();
+ // On either of these resets we expect captures to be all zero and enables to be off.
+ expected_alert_dump = '0;
+ expected_cpu_dump = '0;
+ expected_alert_enable = 0;
+ expected_cpu_enable = 0;
+
reset_test_info = reset_test_infos[start_reset];
cfg.clk_rst_vif.wait_clks(8);
// Wait till rst_lc_n is inactive for non-aon.
wait(cfg.rstmgr_vif.resets_o.rst_lc_n[1]);
- check_reset_info(reset_test_info.expects.code, reset_test_info.description);
- check_alert_info_after_reset('0, 0);
- check_cpu_info_after_reset('0, 0);
+ check_reset_info(reset_test_info.code, reset_test_info.description);
+ check_alert_info_after_reset(expected_alert_dump, expected_alert_enable);
+ check_cpu_info_after_reset(expected_cpu_dump, expected_cpu_enable);
+ prev_alert_dump = expected_alert_dump;
+ prev_cpu_dump = expected_cpu_dump;
for (int i = 0; i < num_trans; ++i) begin
+ logic clear_enables;
+ logic update_capture_dump;
+
`uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM)
`DV_CHECK_RANDOMIZE_FATAL(this)
- set_alert_info_for_capture(alert_dump, enable_alert_info);
- set_cpu_info_for_capture(cpu_dump, enable_cpu_info);
- csr_wr(.ptr(ral.reset_info), .value('1));
- reset_test_info = reset_test_infos[which_reset];
-
if (i == trans_before_enabling_cpu_rst_response) begin
update_cpu_to_sys_rst_release_response(.enable(1));
capture = 1;
end
- expected_reset_info_code = reset_test_info.expects.code;
- expected_alert_enable = enable_alert_info && (!capture || reset_test_info.expects.enable);
- expected_cpu_enable = enable_cpu_info && (!capture || reset_test_info.expects.enable);
+ set_alert_info_for_capture(alert_dump, alert_enable);
+ set_cpu_info_for_capture(cpu_dump, cpu_enable);
+ csr_wr(.ptr(ral.reset_info), .value('1));
+
+ reset_test_info = reset_test_infos[which_reset];
+ clear_enables = aon_reset(which_reset) || (capture && clear_capture_enable(which_reset));
+ update_capture_dump = capture && !aon_reset(which_reset);
+
+ expected_reset_info_code = (capture || aon_reset(which_reset)) ? reset_test_info.code : '0;
+ expected_alert_enable = alert_enable && !clear_enables;
+ expected_cpu_enable = cpu_enable && !clear_enables;
+ // This is expedient, since aon resets will clear any dumps.
+ if (aon_reset(which_reset)) begin
+ prev_alert_dump = '0;
+ prev_cpu_dump = '0;
+ end
+ expected_alert_dump = (alert_enable && update_capture_dump) ? alert_dump : prev_alert_dump;
+ expected_cpu_dump = (cpu_enable && update_capture_dump) ? cpu_dump : prev_cpu_dump;
+
+ `uvm_info(`gfn, $sformatf(
+ "%0s with global capturing %0sbled, alert_en %b, cpu_en %b",
+ which_reset.name(),
+ (capture ? "en" : "dis"),
+ alert_enable,
+ cpu_enable
+ ), UVM_MEDIUM)
+
+ send_sw_reset(sw_reset_csr);
case (which_reset)
- ResetPOR, ResetScan: begin
- // This resets the info registers, which means the previous info contents become zero.
- prev_alert_dump = '0;
- prev_cpu_dump = '0;
- expected_alert_enable = 0;
- expected_cpu_enable = 0;
- if (which_reset == ResetPOR) por_reset();
- else if (which_reset == ResetScan) send_scan_reset();
- end
+ ResetPOR: por_reset();
+ ResetScan: send_scan_reset();
ResetLowPower: send_reset(pwrmgr_pkg::LowPwrEntry, 0);
ResetNdm: send_ndm_reset();
- ResetSw: send_sw_reset();
+ ResetSw: `DV_CHECK_EQ(sw_reset_csr, MuBi4True)
ResetHw: begin
- expected_reset_info_code = {'0, rstreqs, 4'b0};
+ if (capture) expected_reset_info_code = {'0, rstreqs, 4'b0};
send_reset(pwrmgr_pkg::HwReq, rstreqs);
end
default: `uvm_fatal(`gfn, $sformatf("Unexpected reset type %0d", which_reset))
@@ -134,29 +174,13 @@
cfg.clk_rst_vif.wait_clks(8);
wait(cfg.rstmgr_vif.resets_o.rst_lc_n[1]);
- if (!capture) begin
- `uvm_info(`gfn, $sformatf("In no capture %0d", i), UVM_MEDIUM)
- check_reset_info(which_reset inside {ResetPOR, ResetScan} ? expected_reset_info_code : 0,
- reset_test_info.description);
- check_alert_info_after_reset(.alert_dump('0), .enable(expected_alert_enable));
- check_cpu_info_after_reset(.cpu_dump('0), .enable(expected_cpu_enable));
- end else begin
- `uvm_info(`gfn, $sformatf("In capture %0d", i), UVM_MEDIUM)
- check_reset_info(expected_reset_info_code, reset_test_info.description);
-
- if (reset_test_info.expects.update && enable_alert_info) begin
- check_alert_info_after_reset(alert_dump, expected_alert_enable);
- prev_alert_dump = alert_dump;
- end else begin
- check_alert_info_after_reset(prev_alert_dump, expected_alert_enable);
- end
-
- if (reset_test_info.expects.update && enable_cpu_info) begin
- check_cpu_info_after_reset(cpu_dump, expected_cpu_enable);
- prev_cpu_dump = cpu_dump;
- end else begin
- check_cpu_info_after_reset(prev_cpu_dump, expected_cpu_enable);
- end
+ check_reset_info(expected_reset_info_code, reset_test_info.description);
+ check_alert_info_after_reset(.alert_dump(expected_alert_dump),
+ .enable(expected_alert_enable));
+ check_cpu_info_after_reset(.cpu_dump(expected_cpu_dump), .enable(expected_cpu_enable));
+ if (capture) begin
+ prev_alert_dump = expected_alert_dump;
+ prev_cpu_dump = expected_cpu_dump;
end
end
csr_wr(.ptr(ral.reset_info), .value('1));
diff --git a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv
index ea0ce00..4594577 100644
--- a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv
+++ b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv
@@ -69,7 +69,7 @@
set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump);
// Send sw reset.
- send_sw_reset();
+ send_sw_reset(MuBi4True);
check_reset_info(8, "Expected reset_info to indicate sw reset");
check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 0);
