| commit | d498f91d69f914073670b4a5cfc838bb6378083a | [log] [tgz] |
|---|---|---|
| author | Prajwala Puttappa <prajwalaputtappa@lowrisc.org> | Mon May 16 12:54:45 2022 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Wed May 18 07:44:30 2022 +0100 |
| tree | a10291a1647de7f928497e8ada0fda1a7377c3f9 | |
| parent | 7a3a5ec8561829cb0d4184082fa75da38905081c [diff] |
[otbn, dv] Fixes insn_cnt mismatch issue when error occurs in idle state This commit fixes insn count mismatch issue occuring due to a bug inside ISS model when an error is injected when OTBN is in idle state. Instruction counter is cleared on the first clock after the FSM state goes to LOCKED from IDLE. Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
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Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).