commit acfd5d07d1ccc5dce3a588ae67ba8ba4f0f2b4f3
author Drew Macrae <drewmacrae@google.com> Mon Oct 31 22:39:44 2022 -0400
committer Drew Macrae <drewmacrae@gmail.com> Wed Nov 02 09:44:00 2022 -0400
tree ef1fc847be19f2d3ba8138ce60011d18a843290f
parent 321958e43d5af07b8b81162352c8829a9de79760

[bazel] Build verilated model with -j 4 by default

CI should still be constrained where it's run on smaller VMs

Signed-off-by: Drew Macrae <drewmacrae@google.com>

ci/scripts/build-chip-verilator.sh

diff --git a/ci/scripts/build-chip-verilator.sh b/ci/scripts/build-chip-verilator.sh
index 5c4c76d..1d6d374 100755
--- a/ci/scripts/build-chip-verilator.sh
+++ b/ci/scripts/build-chip-verilator.sh
@@ -22,6 +22,7 @@
         fusesoc_core=lowrisc:dv:chip_verilator_sim
         vname=Vchip_sim_tb
         verilator_options="--threads 4"
+        make_options="-j 4"
         ;;
     englishbreakfast)
         fileset=fileset_topgen
@@ -29,7 +30,7 @@
         vname=Vchip_englishbreakfast_verilator
         # Englishbreakfast on CI runs on a 2-core CPU
         verilator_options="--threads 2"
-
+        make_options="-j 2"
         util/topgen-fusesoc.py --files-root=. --topname=top_englishbreakfast
         ;;
     *)
@@ -51,7 +52,8 @@
   run --flag=$fileset --target=sim --setup --build \
   --build-root="$OBJ_DIR/hw" \
   $fusesoc_core \
-  --verilator_options="${verilator_options}"
+  --verilator_options="${verilator_options}" \
+  --make_options="${make_options}"
 
 cp "$OBJ_DIR/hw/sim-verilator/${vname}" \
    "$BIN_DIR/hw/top_${tl}/Vchip_${tl}_verilator"

ci/scripts/run-verilator-tests.sh

diff --git a/ci/scripts/run-verilator-tests.sh b/ci/scripts/run-verilator-tests.sh
index f99e03b..c136a9e 100755
--- a/ci/scripts/run-verilator-tests.sh
+++ b/ci/scripts/run-verilator-tests.sh
@@ -15,6 +15,7 @@
     --test_tag_filters=verilator,-broken \
     --test_output=errors \
     --//hw:verilator_options=--threads,1 \
+    --//hw:make_options=-j,1 \
     //sw/device/tests:aes_smoketest_sim_verilator \
     //sw/device/tests:uart_smoketest_sim_verilator \
     //sw/device/tests:crt_test_sim_verilator \