| commit | abc2374f68088ff5b81a1cb44107948ef2a049f5 | [log] [tgz] |
|---|---|---|
| author | Pirmin Vogel <vogelpi@lowrisc.org> | Sun Jan 31 11:42:43 2021 +0100 |
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | Tue Feb 02 18:31:24 2021 +0100 |
| tree | ceb7a3117048f723ee6f7fdb7eec878049edd05d | |
| parent | e6ca872bf76a9c6c9a794be7ce5a6d164f12ab7b [diff] |
[aes] Improve DOM S-Box First experiments on FPGA revealed that the previous design suffered from substantial leakage resulting from mixing new input data and randomness with previous intermediate results. Basically, the output of the DOM S-Box is only valid in the 5th cycle. Before that, outputs shouldn't toggle and internal nodes should only toggle when the corresponding stage is actually evaluated, i.e. if the data produced during that cycle contributes to the output. To counter those issues, this commit adds pipeline registers to the DOM multiplier primitives (optional according to paper) and inserts additional register stages inside the GF(2^8) and GF(2^4) inverters to only present new input data to the multipliers when they actually need it. Similarly, fresh randomness is only presented to the multipliers when it is actually needed. This requires local PRD buffering but at the same time allows to reduce the width of the masking PRNG by a factor of 4. Also, the PRNG is operated during 4 instead of just 1 cycle per round which is beneficial in terms of SCA resistance. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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