tree: 5d841642006f381404ea7cf6bf04131ee7c9cd92 [path history] [tgz]
  1. __init__.py
  2. data.py
  3. field_enums.py
  4. fpv_csr.sv.tpl
  5. gen_cfg_html.py
  6. gen_cheader.py
  7. gen_ctheader.py
  8. gen_dv.py
  9. gen_fpv.py
  10. gen_html.py
  11. gen_json.py
  12. gen_rtl.py
  13. gen_selfdoc.py
  14. README.md
  15. reg_html.css
  16. reg_pkg.sv.tpl
  17. reg_top.sv.tpl
  18. uvm_reg.sv.tpl
  19. validate.py
  20. version.py
util/reggen/README.md

Register generator reggen and regtool

The utility script regtool.py and collateral under reggen are Python tools to read register descriptions in Hjson and generate various output formats. The tool can output HTML documentation, standard JSON, compact standard JSON (whitespace removed) and Hjson. The example commands assume $REPO_TOP is set to the toplevel directory of the repository.

Setup

If packages have not previously been installed you will need to set a few things up. First use pip3 to install some required packages:

$ pip3 install --user hjson
$ pip3 install --user mistletoe
$ pip3 install --user mako

Register JSON Format

For details on the register JSON format, see the [register tool documentation]({{< relref “doc/rm/register_tool/index.md” >}}). To ensure things stay up to date, the register JSON format information is documented by the tool itself. The documentation can be generated by running the following commands:

$ cd $REPO_TOP/util
$ ./build_docs.py

Under the hood, the build_docs.py tool will automatically use the reggen tool to produce Markdown and processing that into HTML.

Examples using standalone regtool

Normally for documentation the build_docs.py tool will automatically use reggen. The script regtool.py provides a standalone way to run reggen. See the [register tool documentation]({{< relref “doc/rm/register_tool/index.md” >}}) for details about how to invoke the tool.

The following shows an example of how to generate RTL from a register description:

$ cd $REPO_TOP/util
$ mkdir /tmp/rtl
$ ./regtool.py -r -t /tmp/rtl ../hw/ip/uart/data/uart.hjson
$ ls /tmp/rtl
    uart_reg_pkg.sv   uart_reg_top.sv

The following shows an example of how to generate a DV UVM class from a register description:

$ cd $REPO_TOP/util
$ mkdir /tmp/dv
$ ./regtool.py -s -t /tmp/dv ../hw/ip/uart/data/uart.hjson
$ ls /tmp/dv
    uart_reg_block.sv

The following shows an example of how to generate a FPV csr read write assertion module from a register description:

$ cd $REPO_TOP/util
$ mkdir /tmp/fpv/vip
$ ./regtool.py -f -t /tmp/fpv/vip ../hw/ip/uart/data/uart.hjson
$ ls /tmp/fpv
    uart_csr_assert_fpv.sv

If the target directory is not specified, the tool creates the DV file under the hw/ip/{module}/dv/ directory.