| commit | aadb1e3828fa28560c0c680f6571505e6ab782f4 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Fri Aug 28 17:16:28 2020 +0100 |
| committer | Philipp Wagner <mail@philipp-wagner.com> | Thu Sep 03 11:06:23 2020 +0100 |
| tree | 97058f28f98656167ae13fd0310dd8f0cfa78b4e | |
| parent | b4f302c8b2c9bb182c42e6ea137aba13fecf714c [diff] |
[otbn] Do instruction decoding in otbnsim based on insns.yml
This moves away from using the @isa class decorator that riscvmodel
used and instead punts decoding to the code in otbn/util/shared. Now,
we can be reasonably certain that everything matches!
This can actually run a program generated by RIG:
$ hw/ip/otbn/util/otbn-rig gen --size 10 | \
hw/ip/otbn/util/otbn-rig asm -o tst
$ hw/ip/otbn/util/otbn-as tst.S -o tst.o
$ hw/ip/otbn/util/otbn-ld -o tst -T tst.ld tst.o
$ hw/ip/otbn/dv/otbnsim/standalone.py -v tst
addi x30, x0, 1269 | [x30 = 000004f5]
jal x6, 3324 | [x6 = 00000008, pc = 3324]
andi x24, x0, 4 | [x24 = 00000000]
jal x3, 724 | [x3 = 00000d04, pc = 724]
lui x29, 29447 | [x29 = 07307000]
srl x18, x30, x30 | [x18 = 00000000]
slli x17, x24, 5 | [x17 = 00000000]
ecall | []
Whoop!
The change to base-insns.yml is to align the operand names for XORI
with those for the other Reg+Imm instructions. I think all of these
"grs1" names should become just "grs", but I'll push that as a
separate PR.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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