commit a964c077f41ef6a9ff1a68b42dd40d73dfefc7a0
author Michael Schaffner <msf@google.com> Fri Jul 09 14:37:57 2021 -0700
committer tjaychen <timothytim@google.com> Mon Jul 12 16:21:11 2021 -0700
tree 45f86ee2600e3824eab7cc1ea916f008e9b21108
parent 70151fe5370f2b454b8ba53ba699d7bd1345b8d9

[syn] Correct SDC constraints to align with recent ast updates

Signed-off-by: Michael Schaffner <msf@google.com>

hw/top_earlgrey/syn/asic.constraints.sdc

diff --git a/hw/top_earlgrey/syn/asic.constraints.sdc b/hw/top_earlgrey/syn/asic.constraints.sdc
index 931ae44..7225e6a 100644
--- a/hw/top_earlgrey/syn/asic.constraints.sdc
+++ b/hw/top_earlgrey/syn/asic.constraints.sdc
@@ -27,7 +27,7 @@
 #####################
 # main clock        #
 #####################
-set MAIN_CLK_PIN u_ast/u_sys_clk/u_sys_osc/u_buf/out_o
+set MAIN_CLK_PIN u_ast/u_sys_clk/u_sys_osc/u_buf/clk_o
 set MAIN_RST_PIN IO_RST_N
 # target is 100MHz, overconstrain by factor
 set MAIN_TCK_TARGET_PERIOD  10
@@ -43,7 +43,7 @@
 #####################
 # USB clock         #
 #####################
-set USB_CLK_PIN u_ast/u_usb_clk/u_usb_osc/u_buf/out_o
+set USB_CLK_PIN u_ast/u_usb_clk/u_usb_osc/u_buf/clk_o
 # target is 48MHz, overconstrain by 5%
 set USB_TCK_TARGET_PERIOD 20.8
 set USB_TCK_PERIOD [expr $USB_TCK_TARGET_PERIOD*$CLK_PERIOD_FACTOR]
@@ -60,7 +60,7 @@
 #####################
 # IO clk            #
 #####################
-set IO_CLK_PIN u_ast/u_io_clk/u_io_osc/u_buf/out_o
+set IO_CLK_PIN u_ast/u_io_clk/u_io_osc/u_buf/clk_o
 # target is 96MHz, overconstrain by factor
 set IO_TCK_TARGET_PERIOD 10.416
 set IO_TCK_PERIOD [expr $IO_TCK_TARGET_PERIOD*$CLK_PERIOD_FACTOR]
@@ -115,7 +115,7 @@
 #####################
 # AON clk           #
 #####################
-set AON_CLK_PIN u_ast/u_aon_clk/u_aon_osc/u_buf/out_o
+set AON_CLK_PIN u_ast/u_aon_clk/u_aon_osc/u_buf/clk_o
 # target is 200KHz, overconstrain by factor
 set AON_TCK_TARGET_PERIOD 5000.0
 set AON_TCK_PERIOD [expr $AON_TCK_TARGET_PERIOD*$CLK_PERIOD_FACTOR]