[top] RST/CLK pinout alignment in ASIC top
This removes the external clock pad, and renames the reset pad.
The external clock will become a muxed pin in the future.
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/pinmux/rtl/padring.sv b/hw/ip/pinmux/rtl/padring.sv
index b277694..6ca2b29 100644
--- a/hw/ip/pinmux/rtl/padring.sv
+++ b/hw/ip/pinmux/rtl/padring.sv
@@ -12,14 +12,17 @@
module padring import pinmux_reg_pkg::*; #(
// This allows to selectively connect Pad instances.
// unconnected inputs are tied to 0, unconnected outputs are high-z.
- parameter logic [NMioPads-1:0] ConnectMioIn = '1,
- parameter logic [NMioPads-1:0] ConnectMioOut = '1,
- parameter logic [NDioPads-1:0] ConnectDioIn = '1,
- parameter logic [NDioPads-1:0] ConnectDioOut = '1,
+ parameter bit ConnectClk = 1,
+ parameter bit ConnectRst = 1,
+ parameter bit [1:0] ConnectCc = '1,
+ parameter bit [NMioPads-1:0] ConnectMioIn = '1,
+ parameter bit [NMioPads-1:0] ConnectMioOut = '1,
+ parameter bit [NDioPads-1:0] ConnectDioIn = '1,
+ parameter bit [NDioPads-1:0] ConnectDioOut = '1,
// 0: bidir, 1: input, 2: tolerant, 3: open drain
- parameter logic [NMioPads-1:0][1:0] MioPadVariant = '0,
- parameter logic [NDioPads-1:0][1:0] DioPadVariant = '0
+ parameter bit [NMioPads-1:0][1:0] MioPadVariant = '0,
+ parameter bit [NDioPads-1:0][1:0] DioPadVariant = '0
) (
// pad input
input wire clk_pad_i,
@@ -56,34 +59,46 @@
// connection of input wire to an inout pad causes lint problems
// (even though oe is hardwired to 0).
wire clk, rst_n;
- assign clk = clk_pad_i;
- assign rst_n = rst_pad_ni;
+ assign clk = clk_pad_i;
+ assign rst_n = rst_pad_ni;
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( 1 ) // input-only
- ) u_clk_pad (
- .inout_io ( clk ),
- .in_o ( clk_o ),
- .ie_i ( 1'b1 ),
- .out_i ( 1'b0 ),
- .oe_i ( 1'b0 ),
- .attr_i ( '0 ),
- .warl_o ( )
- );
+ if (ConnectClk) begin : gen_clk_pad
+ prim_pad_wrapper #(
+ .AttrDw ( AttrDw ),
+ .Variant ( 1 ) // input-only
+ ) u_clk_pad (
+ .inout_io ( clk ),
+ .in_o ( clk_o ),
+ .ie_i ( 1'b1 ),
+ .out_i ( 1'b0 ),
+ .oe_i ( 1'b0 ),
+ .attr_i ( '0 ),
+ .warl_o ( )
+ );
+ end else begin : gen_no_clk_pad
+ logic unused_clk;
+ assign unused_clk = clk;
+ assign clk_o = 1'b0;
+ end
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( 1 ) // input-only
- ) u_rst_pad (
- .inout_io ( rst_n ),
- .in_o ( rst_no ),
- .ie_i ( 1'b1 ),
- .out_i ( 1'b0 ),
- .oe_i ( 1'b0 ),
- .attr_i ( '0 ),
- .warl_o ( )
- );
+ if (ConnectRst) begin : gen_rst_pad
+ prim_pad_wrapper #(
+ .AttrDw ( AttrDw ),
+ .Variant ( 1 ) // input-only
+ ) u_rst_pad (
+ .inout_io ( rst_n ),
+ .in_o ( rst_no ),
+ .ie_i ( 1'b1 ),
+ .out_i ( 1'b0 ),
+ .oe_i ( 1'b0 ),
+ .attr_i ( '0 ),
+ .warl_o ( )
+ );
+ end else begin : gen_no_rst_pad
+ logic unused_rst;
+ assign unused_rst = rst_n;
+ assign rst_no = 1'b0;
+ end
//////////////////
// Pads for DCD //
@@ -95,31 +110,41 @@
assign cc1 = cc1_i;
assign cc2 = cc2_i;
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( 1 ) // input-only
- ) u_cc1_pad (
- .inout_io ( cc1 ),
- .in_o ( ),
- .ie_i ( 1'b0 ), // input buffer disabled
- .out_i ( 1'b0 ),
- .oe_i ( 1'b0 ),
- .attr_i ( '0 ),
- .warl_o ( )
- );
+ if (ConnectCc[0]) begin : gen_cc1_pad
+ prim_pad_wrapper #(
+ .AttrDw ( AttrDw ),
+ .Variant ( 1 ) // input-only
+ ) u_cc1_pad (
+ .inout_io ( cc1 ),
+ .in_o ( ),
+ .ie_i ( 1'b0 ), // input buffer disabled
+ .out_i ( 1'b0 ),
+ .oe_i ( 1'b0 ),
+ .attr_i ( '0 ),
+ .warl_o ( )
+ );
+ end else begin : gen_no_cc1_pad
+ logic unused_cc1;
+ assign unused_cc1 = cc1;
+ end
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( 1 ) // input-only
- ) u_cc2_pad (
- .inout_io ( cc2 ),
- .in_o ( ),
- .ie_i ( 1'b0 ), // input buffer disabled
- .out_i ( 1'b0 ),
- .oe_i ( 1'b0 ),
- .attr_i ( '0 ),
- .warl_o ( )
- );
+ if (ConnectCc[1]) begin : gen_cc2_pad
+ prim_pad_wrapper #(
+ .AttrDw ( AttrDw ),
+ .Variant ( 1 ) // input-only
+ ) u_cc2_pad (
+ .inout_io ( cc2 ),
+ .in_o ( ),
+ .ie_i ( 1'b0 ), // input buffer disabled
+ .out_i ( 1'b0 ),
+ .oe_i ( 1'b0 ),
+ .attr_i ( '0 ),
+ .warl_o ( )
+ );
+ end else begin : gen_no_cc2_pad
+ logic unused_cc2;
+ assign unused_cc2 = cc2;
+ end
//////////////
// MIO Pads //
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index 9749ea4..b9c922d 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -84,10 +84,12 @@
bind `FLASH1_INFO_HIER mem_bkdr_if flash1_info_bkdr_if();
bind `OTP_MEM_HIER mem_bkdr_if otp_bkdr_if();
+ // TODO: the external clk is currently not connected.
+ // We will need to feed this in via a muxed pin, once that function implemented.
+
top_earlgrey_asic dut (
// Clock and Reset
- .IO_CLK(clk),
- .IO_RST_N(rst_n),
+ .POR_N(rst_n),
// Bank A (VIOA domain)
.SPI_HOST_D0(spi_host_tie_off[0]),
.SPI_HOST_D1(spi_host_tie_off[1]),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
index daf0311..b41161b 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
@@ -4,10 +4,7 @@
module top_earlgrey_asic (
// Clock and Reset
- // TODO: remove the IO_CLK port once AST contains an oscillator model. a calibration clock
- // will then be muxed in via another port.
- inout IO_CLK,
- inout IO_RST_N,
+ inout POR_N,
// Bank A (VIOA domain)
inout SPI_HOST_D0,
inout SPI_HOST_D1,
@@ -90,7 +87,7 @@
// Padring Instance //
//////////////////////
- logic clk, rst_n;
+ logic rst_n;
logic [pinmux_reg_pkg::NMioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] mio_attr;
logic [pinmux_reg_pkg::NDioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] dio_attr;
logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_core, mio_out_padring;
@@ -106,8 +103,12 @@
wire unused_usbdev_d, unused_usbdev_aon_sense;
wire unused_usbdev_dp_pullup_en, unused_usbdev_dn_pullup_en;
wire unused_spi_device_s2, unused_spi_device_s3;
+ wire unused_clk;
padring #(
+ // The clock pad is not connected since
+ // AST contains an internal oscillator model.
+ .ConnectClk ( 0 ),
// All MIOs are connected
.ConnectMioIn ( 44'hFFF_FFFF_FFFF ),
.ConnectMioOut ( 44'hFFF_FFFF_FFFF ),
@@ -190,12 +191,12 @@
} )
) u_padring (
// Clk / Rst
- .clk_pad_i ( IO_CLK ),
- .rst_pad_ni ( IO_RST_N ),
- .clk_o ( clk ),
- .rst_no ( rst_n ),
- .cc1_i ( CC1 ),
- .cc2_i ( CC2 ),
+ .clk_pad_i ( unused_clk ),
+ .rst_pad_ni ( POR_N ),
+ .clk_o ( ),
+ .rst_no ( rst_n ),
+ .cc1_i ( CC1 ),
+ .cc2_i ( CC2 ),
// "special"
// MIO Pads
.mio_pad_io ( { // RBox
@@ -452,6 +453,10 @@
import rstmgr_pkg::DomainAonSel;
import rstmgr_pkg::Domain0Sel;
+ // TODO: need to mux the external clock.
+ logic ext_clk;
+ assign ext_clk = 1'b0;
+
ast #(
.EntropyStreams(top_pkg::ENTROPY_STREAM),
.AdcChannels(top_pkg::ADC_CHANNELS),
@@ -477,7 +482,7 @@
.rst_ast_tlul_ni ( rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
.clk_ast_usb_i ( clks_ast.clk_ast_usbdev_usb_peri ),
.rst_ast_usb_ni ( rsts_ast.rst_ast_usbdev_usb_n[Domain0Sel] ),
- .clk_ast_ext_i ( clk ),
+ .clk_ast_ext_i ( ext_clk ),
.por_ni ( rst_n ),
// pok test for FPGA
.vcc_supp_i ( 1'b1 ),
