[dif/rv_plic] Integrate autogen'd DIF artifacts into src tree.
This commit partially addresses #8142. Specifically it:
1. deprecates existing (manually implemented) **RV PLIC**
specific DIF return codes and toggle type,
2. integrates the auto-generated **RV PLIC** DIFs into meson build
targets, and
3. refactors all existing source code to make use of the new shared DIF
types and error codes.
This continues the long-term goal of auto-generating several DIF
components across all IPs, as described in #8142.
Signed-off-by: Timothy Trippel <ttrippel@google.com>
diff --git a/sw/device/lib/dif/autogen/meson.build b/sw/device/lib/dif/autogen/meson.build
index 69b0ed8..bc6544c 100644
--- a/sw/device/lib/dif/autogen/meson.build
+++ b/sw/device/lib/dif/autogen/meson.build
@@ -254,6 +254,20 @@
)
)
+# Autogen RV PLIC DIF library
+sw_lib_dif_autogen_rv_plic = declare_dependency(
+ link_with: static_library(
+ 'sw_lib_dif_autogen_rv_plic',
+ sources: [
+ hw_top_earlgrey_rv_plic_reg_h,
+ 'dif_rv_plic_autogen.c',
+ ],
+ dependencies: [
+ sw_lib_mmio,
+ ],
+ )
+)
+
# Autogen SPI Device DIF library
sw_lib_dif_autogen_spi_device = declare_dependency(
link_with: static_library(
diff --git a/sw/device/lib/dif/dif_rv_plic.c b/sw/device/lib/dif/dif_rv_plic.c
index 729d818..e7cff68 100644
--- a/sw/device/lib/dif/dif_rv_plic.c
+++ b/sw/device/lib/dif/dif_rv_plic.c
@@ -128,7 +128,7 @@
// Clear all of the priority registers.
for (int i = 0; i < RV_PLIC_PARAM_NUM_SRC; ++i) {
ptrdiff_t offset = plic_priority_reg_offset(i);
- mmio_region_write32(plic->params.base_addr, offset, 0);
+ mmio_region_write32(plic->base_addr, offset, 0);
}
// Clear all of the target related registers.
@@ -138,189 +138,187 @@
ptrdiff_t offset = plic_irq_enable_base_for_target(target);
for (int i = 0; i < RV_PLIC_IE0_MULTIREG_COUNT; ++i) {
ptrdiff_t multireg_offset = offset + (i * sizeof(uint32_t));
- mmio_region_write32(plic->params.base_addr, multireg_offset, 0);
+ mmio_region_write32(plic->base_addr, multireg_offset, 0);
}
// Clear threshold registers.
offset = plic_threshold_base_for_target(target);
- mmio_region_write32(plic->params.base_addr, offset, 0);
+ mmio_region_write32(plic->base_addr, offset, 0);
// Clear software interrupt registers.
offset = plic_software_irq_base_for_target(target);
- mmio_region_write32(plic->params.base_addr, offset, 0);
+ mmio_region_write32(plic->base_addr, offset, 0);
}
}
-dif_rv_plic_result_t dif_rv_plic_init(dif_rv_plic_params_t params,
- dif_rv_plic_t *plic) {
+dif_result_t dif_rv_plic_init(mmio_region_t base_addr, dif_rv_plic_t *plic) {
if (plic == NULL) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
- plic->params = params;
+ plic->base_addr = base_addr;
// TODO: Move this out into its own function.
plic_reset(plic);
- return kDifRvPlicOk;
+ return kDifOk;
}
-dif_rv_plic_result_t dif_rv_plic_irq_get_enabled(const dif_rv_plic_t *plic,
- dif_rv_plic_irq_id_t irq,
- dif_rv_plic_target_t target,
- dif_rv_plic_toggle_t *state) {
+dif_result_t dif_rv_plic_irq_get_enabled(const dif_rv_plic_t *plic,
+ dif_rv_plic_irq_id_t irq,
+ dif_rv_plic_target_t target,
+ dif_toggle_t *state) {
if (plic == NULL || irq >= RV_PLIC_PARAM_NUM_SRC ||
target >= RV_PLIC_PARAM_NUM_TARGET) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
plic_reg_info_t reg_info = plic_irq_enable_reg_info(irq, target);
- uint32_t reg = mmio_region_read32(plic->params.base_addr, reg_info.offset);
+ uint32_t reg = mmio_region_read32(plic->base_addr, reg_info.offset);
bool is_enabled = bitfield_bit32_read(reg, reg_info.bit_index);
- *state = is_enabled ? kDifRvPlicToggleEnabled : kDifRvPlicToggleDisabled;
+ *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
- return kDifRvPlicOk;
+ return kDifOk;
}
-dif_rv_plic_result_t dif_rv_plic_irq_set_enabled(const dif_rv_plic_t *plic,
- dif_rv_plic_irq_id_t irq,
- dif_rv_plic_target_t target,
- dif_rv_plic_toggle_t state) {
+dif_result_t dif_rv_plic_irq_set_enabled(const dif_rv_plic_t *plic,
+ dif_rv_plic_irq_id_t irq,
+ dif_rv_plic_target_t target,
+ dif_toggle_t state) {
if (plic == NULL || irq >= RV_PLIC_PARAM_NUM_SRC ||
target >= RV_PLIC_PARAM_NUM_TARGET) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
bool flag;
switch (state) {
- case kDifRvPlicToggleEnabled:
+ case kDifToggleEnabled:
flag = true;
break;
- case kDifRvPlicToggleDisabled:
+ case kDifToggleDisabled:
flag = false;
break;
default:
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
plic_reg_info_t reg_info = plic_irq_enable_reg_info(irq, target);
- uint32_t reg = mmio_region_read32(plic->params.base_addr, reg_info.offset);
+ uint32_t reg = mmio_region_read32(plic->base_addr, reg_info.offset);
reg = bitfield_bit32_write(reg, reg_info.bit_index, flag);
- mmio_region_write32(plic->params.base_addr, reg_info.offset, reg);
+ mmio_region_write32(plic->base_addr, reg_info.offset, reg);
- return kDifRvPlicOk;
+ return kDifOk;
}
-dif_rv_plic_result_t dif_rv_plic_irq_set_priority(const dif_rv_plic_t *plic,
- dif_rv_plic_irq_id_t irq,
- uint32_t priority) {
+dif_result_t dif_rv_plic_irq_set_priority(const dif_rv_plic_t *plic,
+ dif_rv_plic_irq_id_t irq,
+ uint32_t priority) {
if (plic == NULL || irq >= RV_PLIC_PARAM_NUM_SRC ||
priority > kDifRvPlicMaxPriority) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
ptrdiff_t offset = plic_priority_reg_offset(irq);
- mmio_region_write32(plic->params.base_addr, offset, priority);
+ mmio_region_write32(plic->base_addr, offset, priority);
- return kDifRvPlicOk;
+ return kDifOk;
}
-dif_rv_plic_result_t dif_rv_plic_target_set_threshold(
- const dif_rv_plic_t *plic, dif_rv_plic_target_t target,
- uint32_t threshold) {
+dif_result_t dif_rv_plic_target_set_threshold(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target,
+ uint32_t threshold) {
if (plic == NULL || target >= RV_PLIC_PARAM_NUM_TARGET ||
threshold > kDifRvPlicMaxPriority) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
ptrdiff_t threshold_offset = plic_threshold_base_for_target(target);
- mmio_region_write32(plic->params.base_addr, threshold_offset, threshold);
+ mmio_region_write32(plic->base_addr, threshold_offset, threshold);
- return kDifRvPlicOk;
+ return kDifOk;
}
-dif_rv_plic_result_t dif_rv_plic_irq_is_pending(const dif_rv_plic_t *plic,
- dif_rv_plic_irq_id_t irq,
- bool *is_pending) {
+dif_result_t dif_rv_plic_irq_is_pending(const dif_rv_plic_t *plic,
+ dif_rv_plic_irq_id_t irq,
+ bool *is_pending) {
if (plic == NULL || irq >= RV_PLIC_PARAM_NUM_SRC || is_pending == NULL) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
plic_reg_info_t reg_info = plic_irq_pending_reg_info(irq);
- uint32_t reg = mmio_region_read32(plic->params.base_addr, reg_info.offset);
+ uint32_t reg = mmio_region_read32(plic->base_addr, reg_info.offset);
*is_pending = bitfield_bit32_read(reg, reg_info.bit_index);
- return kDifRvPlicOk;
+ return kDifOk;
}
-dif_rv_plic_result_t dif_rv_plic_irq_claim(const dif_rv_plic_t *plic,
- dif_rv_plic_target_t target,
- dif_rv_plic_irq_id_t *claim_data) {
+dif_result_t dif_rv_plic_irq_claim(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target,
+ dif_rv_plic_irq_id_t *claim_data) {
if (plic == NULL || target >= RV_PLIC_PARAM_NUM_TARGET ||
claim_data == NULL) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
ptrdiff_t claim_complete_reg = plic_claim_complete_base_for_target(target);
- *claim_data = mmio_region_read32(plic->params.base_addr, claim_complete_reg);
+ *claim_data = mmio_region_read32(plic->base_addr, claim_complete_reg);
- return kDifRvPlicOk;
+ return kDifOk;
}
-dif_rv_plic_result_t dif_rv_plic_irq_complete(
- const dif_rv_plic_t *plic, dif_rv_plic_target_t target,
- dif_rv_plic_irq_id_t complete_data) {
+dif_result_t dif_rv_plic_irq_complete(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target,
+ dif_rv_plic_irq_id_t complete_data) {
if (plic == NULL || target >= RV_PLIC_PARAM_NUM_TARGET) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
// Write back the claimed IRQ ID to the target specific CC register,
// to notify the PLIC of the IRQ completion.
ptrdiff_t claim_complete_reg = plic_claim_complete_base_for_target(target);
- mmio_region_write32(plic->params.base_addr, claim_complete_reg,
- complete_data);
+ mmio_region_write32(plic->base_addr, claim_complete_reg, complete_data);
- return kDifRvPlicOk;
+ return kDifOk;
}
-dif_rv_plic_result_t dif_rv_plic_software_irq_force(
- const dif_rv_plic_t *plic, dif_rv_plic_target_t target) {
+dif_result_t dif_rv_plic_software_irq_force(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target) {
if (plic == NULL || target >= RV_PLIC_PARAM_NUM_TARGET) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
ptrdiff_t msip_offset = plic_software_irq_base_for_target(target);
- mmio_region_write32(plic->params.base_addr, msip_offset, 1);
+ mmio_region_write32(plic->base_addr, msip_offset, 1);
- return kDifRvPlicOk;
+ return kDifOk;
}
-dif_rv_plic_result_t dif_rv_plic_software_irq_acknowledge(
- const dif_rv_plic_t *plic, dif_rv_plic_target_t target) {
+dif_result_t dif_rv_plic_software_irq_acknowledge(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target) {
if (plic == NULL || target >= RV_PLIC_PARAM_NUM_TARGET) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
ptrdiff_t msip_offset = plic_software_irq_base_for_target(target);
- mmio_region_write32(plic->params.base_addr, msip_offset, 0);
+ mmio_region_write32(plic->base_addr, msip_offset, 0);
- return kDifRvPlicOk;
+ return kDifOk;
}
-dif_rv_plic_result_t dif_rv_plic_software_irq_is_pending(
- const dif_rv_plic_t *plic, dif_rv_plic_target_t target, bool *is_pending) {
+dif_result_t dif_rv_plic_software_irq_is_pending(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target,
+ bool *is_pending) {
if (plic == NULL || target >= RV_PLIC_PARAM_NUM_TARGET ||
is_pending == NULL) {
- return kDifRvPlicBadArg;
+ return kDifBadArg;
}
ptrdiff_t msip_offset = plic_software_irq_base_for_target(target);
- uint32_t register_value =
- mmio_region_read32(plic->params.base_addr, msip_offset);
+ uint32_t register_value = mmio_region_read32(plic->base_addr, msip_offset);
*is_pending = (register_value == 1) ? true : false;
- return kDifRvPlicOk;
+ return kDifOk;
}
diff --git a/sw/device/lib/dif/dif_rv_plic.h b/sw/device/lib/dif/dif_rv_plic.h
index d14bfd7..355692a 100644
--- a/sw/device/lib/dif/dif_rv_plic.h
+++ b/sw/device/lib/dif/dif_rv_plic.h
@@ -22,73 +22,15 @@
#include "sw/device/lib/base/macros.h"
#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_base.h"
+
+#include "sw/device/lib/dif/autogen/dif_rv_plic_autogen.h"
#ifdef __cplusplus
extern "C" {
#endif // __cplusplus
/**
- * A toggle state: enabled, or disabled.
- *
- * This enum may be used instead of a `bool` when describing an enabled/disabled
- * state.
- */
-typedef enum dif_rv_plic_toggle {
- /*
- * The "enabled" state.
- */
- kDifRvPlicToggleEnabled,
- /**
- * The "disabled" state.
- */
- kDifRvPlicToggleDisabled,
-} dif_rv_plic_toggle_t;
-
-/**
- * Hardware instantiation parameters for PLIC.
- *
- * This struct describes information about the underlying hardware that is
- * not determined until the hardware design is used as part of a top-level
- * design.
- */
-typedef struct dif_rv_plic_params {
- /**
- * The base address for the PLIC hardware registers.
- */
- mmio_region_t base_addr;
-} dif_rv_plic_params_t;
-
-/**
- * A handle to PLIC.
- *
- * This type should be treated as opaque by users.
- */
-typedef struct dif_rv_plic {
- dif_rv_plic_params_t params;
-} dif_rv_plic_t;
-
-/**
- * The result of a PLIC operation.
- */
-typedef enum dif_rv_plic_result {
- /**
- * Indicates that the operation succeeded.
- */
- kDifRvPlicOk = 0,
- /**
- * Indicates some unspecified failure.
- */
- kDifRvPlicError = 1,
- /**
- * Indicates that some parameter passed into a function failed a
- * precondition.
- *
- * When this value is returned, no hardware operations occurred.
- */
- kDifRvPlicBadArg = 2,
-} dif_rv_plic_result_t;
-
-/**
* The lowest interrupt priority.
*/
extern const uint32_t kDifRvPlicMinPriority;
@@ -133,8 +75,7 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_init(dif_rv_plic_params_t params,
- dif_rv_plic_t *plic);
+dif_result_t dif_rv_plic_init(mmio_region_t base_addr, dif_rv_plic_t *plic);
/**
* Returns whether a particular interrupt is currently pending.
@@ -145,9 +86,9 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_irq_is_pending(const dif_rv_plic_t *plic,
- dif_rv_plic_irq_id_t irq,
- bool *is_pending);
+dif_result_t dif_rv_plic_irq_is_pending(const dif_rv_plic_t *plic,
+ dif_rv_plic_irq_id_t irq,
+ bool *is_pending);
/**
* Checks whether a particular interrupt is currently enabled or disabled.
@@ -159,10 +100,10 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_irq_get_enabled(const dif_rv_plic_t *plic,
- dif_rv_plic_irq_id_t irq,
- dif_rv_plic_target_t target,
- dif_rv_plic_toggle_t *state);
+dif_result_t dif_rv_plic_irq_get_enabled(const dif_rv_plic_t *plic,
+ dif_rv_plic_irq_id_t irq,
+ dif_rv_plic_target_t target,
+ dif_toggle_t *state);
/**
* Sets whether a particular interrupt is currently enabled or disabled.
@@ -177,10 +118,10 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_irq_set_enabled(const dif_rv_plic_t *plic,
- dif_rv_plic_irq_id_t irq,
- dif_rv_plic_target_t target,
- dif_rv_plic_toggle_t state);
+dif_result_t dif_rv_plic_irq_set_enabled(const dif_rv_plic_t *plic,
+ dif_rv_plic_irq_id_t irq,
+ dif_rv_plic_target_t target,
+ dif_toggle_t state);
/**
* Sets IRQ source priority (0-3).
@@ -195,9 +136,9 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_irq_set_priority(const dif_rv_plic_t *plic,
- dif_rv_plic_irq_id_t irq,
- uint32_t priority);
+dif_result_t dif_rv_plic_irq_set_priority(const dif_rv_plic_t *plic,
+ dif_rv_plic_irq_id_t irq,
+ uint32_t priority);
/**
* Sets the target priority threshold.
@@ -212,8 +153,9 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_target_set_threshold(
- const dif_rv_plic_t *plic, dif_rv_plic_target_t target, uint32_t threshold);
+dif_result_t dif_rv_plic_target_set_threshold(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target,
+ uint32_t threshold);
/**
* Claims an IRQ and gets the information about the source.
@@ -240,9 +182,9 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_irq_claim(const dif_rv_plic_t *plic,
- dif_rv_plic_target_t target,
- dif_rv_plic_irq_id_t *claim_data);
+dif_result_t dif_rv_plic_irq_claim(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target,
+ dif_rv_plic_irq_id_t *claim_data);
/**
* Completes the claimed IRQ.
@@ -263,9 +205,9 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_irq_complete(
- const dif_rv_plic_t *plic, dif_rv_plic_target_t target,
- dif_rv_plic_irq_id_t complete_data);
+dif_result_t dif_rv_plic_irq_complete(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target,
+ dif_rv_plic_irq_id_t complete_data);
/**
* Forces the software interrupt for a particular target.
@@ -282,11 +224,11 @@
*
* @param plic PLIC state data.
* @param target Target HART.
- * @return `dif_rv_plic_result_t`.
+ * @return `dif_result_t`.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_software_irq_force(
- const dif_rv_plic_t *plic, dif_rv_plic_target_t target);
+dif_result_t dif_rv_plic_software_irq_force(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target);
/**
* Acknowledges the software interrupt for a particular target.
@@ -297,11 +239,11 @@
*
* @param plic PLIC state data.
* @param target Target HART.
- * @return `dif_rv_plic_result_t`.
+ * @return `dif_result_t`.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_software_irq_acknowledge(
- const dif_rv_plic_t *plic, dif_rv_plic_target_t target);
+dif_result_t dif_rv_plic_software_irq_acknowledge(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target);
/**
* Returns software interrupt pending state for a particular target.
@@ -309,11 +251,12 @@
* @param plic PLIC state data.
* @param target Target HART.
* @param[out] is_pending Flag indicating whether the interrupt is pending.
- * @return `dif_rv_plic_result_t`.
+ * @return `dif_result_t`.
*/
OT_WARN_UNUSED_RESULT
-dif_rv_plic_result_t dif_rv_plic_software_irq_is_pending(
- const dif_rv_plic_t *plic, dif_rv_plic_target_t target, bool *is_pending);
+dif_result_t dif_rv_plic_software_irq_is_pending(const dif_rv_plic_t *plic,
+ dif_rv_plic_target_t target,
+ bool *is_pending);
#ifdef __cplusplus
} // extern "C"
diff --git a/sw/device/lib/dif/dif_rv_plic_unittest.cc b/sw/device/lib/dif/dif_rv_plic_unittest.cc
index 8ef6910..2293653 100644
--- a/sw/device/lib/dif/dif_rv_plic_unittest.cc
+++ b/sw/device/lib/dif/dif_rv_plic_unittest.cc
@@ -30,9 +30,7 @@
class PlicTest : public Test, public MmioTest {
protected:
- dif_rv_plic_t plic_ = {
- .params = {.base_addr = dev().region()},
- };
+ dif_rv_plic_t plic_ = {.base_addr = dev().region()};
};
class InitTest : public PlicTest {
@@ -61,15 +59,13 @@
};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_rv_plic_init({.base_addr = dev().region()}, nullptr),
- kDifRvPlicBadArg);
+ EXPECT_EQ(dif_rv_plic_init(dev().region(), nullptr), kDifBadArg);
}
TEST_F(InitTest, Success) {
ExpectInitReset();
- EXPECT_EQ(dif_rv_plic_init({.base_addr = dev().region()}, &plic_),
- kDifRvPlicOk);
+ EXPECT_EQ(dif_rv_plic_init(dev().region(), &plic_), kDifOk);
}
class IrqTest : public PlicTest {
@@ -152,8 +148,8 @@
TEST_F(IrqEnableSetTest, NullArgs) {
EXPECT_EQ(dif_rv_plic_irq_set_enabled(nullptr, kFirstIrq, kTarget0,
- kDifRvPlicToggleEnabled),
- kDifRvPlicBadArg);
+ kDifToggleEnabled),
+ kDifBadArg);
}
TEST_F(IrqEnableSetTest, Target0Enable) {
@@ -161,9 +157,9 @@
// Enable every IRQ, one at a time.
for (int i = 0; i < RV_PLIC_PARAM_NUM_SRC; ++i) {
- EXPECT_EQ(dif_rv_plic_irq_set_enabled(&plic_, i, kTarget0,
- kDifRvPlicToggleEnabled),
- kDifRvPlicOk);
+ EXPECT_EQ(
+ dif_rv_plic_irq_set_enabled(&plic_, i, kTarget0, kDifToggleEnabled),
+ kDifOk);
}
}
@@ -172,9 +168,9 @@
// Disable every bit, one at a time.
for (int i = 0; i < RV_PLIC_PARAM_NUM_SRC; ++i) {
- EXPECT_EQ(dif_rv_plic_irq_set_enabled(&plic_, i, kTarget0,
- kDifRvPlicToggleDisabled),
- kDifRvPlicOk);
+ EXPECT_EQ(
+ dif_rv_plic_irq_set_enabled(&plic_, i, kTarget0, kDifToggleDisabled),
+ kDifOk);
}
}
@@ -183,13 +179,13 @@
TEST_F(IrqPrioritySetTest, NullArgs) {
EXPECT_EQ(
dif_rv_plic_irq_set_priority(nullptr, kFirstIrq, kDifRvPlicMaxPriority),
- kDifRvPlicBadArg);
+ kDifBadArg);
}
TEST_F(IrqPrioritySetTest, PriorityInvalid) {
EXPECT_EQ(dif_rv_plic_irq_set_priority(nullptr, kFirstIrq,
kDifRvPlicMaxPriority + 1),
- kDifRvPlicBadArg);
+ kDifBadArg);
}
TEST_F(IrqPrioritySetTest, Success) {
@@ -199,7 +195,7 @@
EXPECT_WRITE32(offset, kDifRvPlicMaxPriority);
EXPECT_EQ(dif_rv_plic_irq_set_priority(&plic_, i, kDifRvPlicMaxPriority),
- kDifRvPlicOk);
+ kDifOk);
}
}
@@ -208,13 +204,13 @@
TEST_F(TargetThresholdSetTest, NullArgs) {
EXPECT_EQ(dif_rv_plic_target_set_threshold(nullptr, kTarget0,
kDifRvPlicMaxPriority),
- kDifRvPlicBadArg);
+ kDifBadArg);
}
TEST_F(TargetThresholdSetTest, Target0PriorityInvalid) {
EXPECT_EQ(dif_rv_plic_target_set_threshold(&plic_, kTarget0,
kDifRvPlicMaxPriority + 1),
- kDifRvPlicBadArg);
+ kDifBadArg);
}
TEST_F(TargetThresholdSetTest, Target0Success) {
@@ -222,22 +218,21 @@
EXPECT_EQ(
dif_rv_plic_target_set_threshold(&plic_, kTarget0, kDifRvPlicMaxPriority),
- kDifRvPlicOk);
+ kDifOk);
}
class IrqPendingStatusGetTest : public IrqTest {};
TEST_F(IrqPendingStatusGetTest, NullArgs) {
bool status;
- dif_rv_plic_result_t result =
- dif_rv_plic_irq_is_pending(nullptr, kFirstIrq, &status);
- EXPECT_EQ(result, kDifRvPlicBadArg);
+ dif_result_t result = dif_rv_plic_irq_is_pending(nullptr, kFirstIrq, &status);
+ EXPECT_EQ(result, kDifBadArg);
result = dif_rv_plic_irq_is_pending(&plic_, kFirstIrq, nullptr);
- EXPECT_EQ(result, kDifRvPlicBadArg);
+ EXPECT_EQ(result, kDifBadArg);
result = dif_rv_plic_irq_is_pending(nullptr, kFirstIrq, nullptr);
- EXPECT_EQ(result, kDifRvPlicBadArg);
+ EXPECT_EQ(result, kDifBadArg);
}
TEST_F(IrqPendingStatusGetTest, Enabled) {
@@ -246,9 +241,8 @@
// Get status of every IRQ, one at a time.
for (int i = 0; i < RV_PLIC_PARAM_NUM_SRC; ++i) {
bool status;
- dif_rv_plic_result_t result =
- dif_rv_plic_irq_is_pending(&plic_, i, &status);
- EXPECT_EQ(result, kDifRvPlicOk);
+ dif_result_t result = dif_rv_plic_irq_is_pending(&plic_, i, &status);
+ EXPECT_EQ(result, kDifOk);
EXPECT_TRUE(status);
}
}
@@ -259,9 +253,8 @@
// Get status of every IRQ, one at a time.
for (int i = 0; i < RV_PLIC_PARAM_NUM_SRC; ++i) {
bool status;
- dif_rv_plic_result_t result =
- dif_rv_plic_irq_is_pending(&plic_, i, &status);
- EXPECT_EQ(result, kDifRvPlicOk);
+ dif_result_t result = dif_rv_plic_irq_is_pending(&plic_, i, &status);
+ EXPECT_EQ(result, kDifOk);
EXPECT_FALSE(status);
}
}
@@ -272,12 +265,11 @@
TEST_F(IrqClaimTest, NullArgs) {
dif_rv_plic_irq_id_t data;
- EXPECT_EQ(dif_rv_plic_irq_claim(nullptr, kTarget0, &data), kDifRvPlicBadArg);
+ EXPECT_EQ(dif_rv_plic_irq_claim(nullptr, kTarget0, &data), kDifBadArg);
- EXPECT_EQ(dif_rv_plic_irq_claim(&plic_, kTarget0, nullptr), kDifRvPlicBadArg);
+ EXPECT_EQ(dif_rv_plic_irq_claim(&plic_, kTarget0, nullptr), kDifBadArg);
- EXPECT_EQ(dif_rv_plic_irq_claim(nullptr, kTarget0, nullptr),
- kDifRvPlicBadArg);
+ EXPECT_EQ(dif_rv_plic_irq_claim(nullptr, kTarget0, nullptr), kDifBadArg);
}
TEST_F(IrqClaimTest, Target0Success) {
@@ -289,7 +281,7 @@
// Claim every IRQ, one per a call.
for (int i = 0; i < RV_PLIC_PARAM_NUM_SRC; ++i) {
dif_rv_plic_irq_id_t data;
- EXPECT_EQ(dif_rv_plic_irq_claim(&plic_, kTarget0, &data), kDifRvPlicOk);
+ EXPECT_EQ(dif_rv_plic_irq_claim(&plic_, kTarget0, &data), kDifOk);
EXPECT_EQ(data, i);
}
}
@@ -299,7 +291,7 @@
};
TEST_F(IrqCompleteTest, NullArgs) {
- EXPECT_EQ(dif_rv_plic_irq_complete(nullptr, kTarget0, 0), kDifRvPlicBadArg);
+ EXPECT_EQ(dif_rv_plic_irq_complete(nullptr, kTarget0, 0), kDifBadArg);
}
TEST_F(IrqCompleteTest, Target0Success) {
@@ -310,7 +302,7 @@
// Complete all of the IRQs.
for (int i = 0; i < RV_PLIC_PARAM_NUM_SRC; ++i) {
- EXPECT_EQ(dif_rv_plic_irq_complete(&plic_, kTarget0, i), kDifRvPlicOk);
+ EXPECT_EQ(dif_rv_plic_irq_complete(&plic_, kTarget0, i), kDifOk);
}
}
@@ -319,18 +311,17 @@
};
TEST_F(SoftwareIrqForceTest, NullArgs) {
- EXPECT_EQ(dif_rv_plic_software_irq_force(nullptr, kTarget0),
- kDifRvPlicBadArg);
+ EXPECT_EQ(dif_rv_plic_software_irq_force(nullptr, kTarget0), kDifBadArg);
}
TEST_F(SoftwareIrqForceTest, BadTarget) {
EXPECT_EQ(dif_rv_plic_software_irq_force(&plic_, RV_PLIC_PARAM_NUM_TARGET),
- kDifRvPlicBadArg);
+ kDifBadArg);
}
TEST_F(SoftwareIrqForceTest, Target0Success) {
EXPECT_WRITE32(RV_PLIC_MSIP0_REG_OFFSET, 1);
- EXPECT_EQ(dif_rv_plic_software_irq_force(&plic_, kTarget0), kDifRvPlicOk);
+ EXPECT_EQ(dif_rv_plic_software_irq_force(&plic_, kTarget0), kDifOk);
}
class SoftwareIrqAcknowledgeTest : public PlicTest {
@@ -339,19 +330,18 @@
TEST_F(SoftwareIrqAcknowledgeTest, NullArgs) {
EXPECT_EQ(dif_rv_plic_software_irq_acknowledge(nullptr, kTarget0),
- kDifRvPlicBadArg);
+ kDifBadArg);
}
TEST_F(SoftwareIrqAcknowledgeTest, BadTarget) {
EXPECT_EQ(
dif_rv_plic_software_irq_acknowledge(&plic_, RV_PLIC_PARAM_NUM_TARGET),
- kDifRvPlicBadArg);
+ kDifBadArg);
}
TEST_F(SoftwareIrqAcknowledgeTest, Target0Success) {
EXPECT_WRITE32(RV_PLIC_MSIP0_REG_OFFSET, 0);
- EXPECT_EQ(dif_rv_plic_software_irq_acknowledge(&plic_, kTarget0),
- kDifRvPlicOk);
+ EXPECT_EQ(dif_rv_plic_software_irq_acknowledge(&plic_, kTarget0), kDifOk);
}
class SoftwareIrqIsPendingTest : public PlicTest {
@@ -360,21 +350,21 @@
TEST_F(SoftwareIrqIsPendingTest, NullArgs) {
EXPECT_EQ(dif_rv_plic_software_irq_is_pending(nullptr, kTarget0, nullptr),
- kDifRvPlicBadArg);
+ kDifBadArg);
EXPECT_EQ(dif_rv_plic_software_irq_is_pending(&plic_, kTarget0, nullptr),
- kDifRvPlicBadArg);
+ kDifBadArg);
bool is_pending;
EXPECT_EQ(dif_rv_plic_software_irq_is_pending(nullptr, kTarget0, &is_pending),
- kDifRvPlicBadArg);
+ kDifBadArg);
}
TEST_F(SoftwareIrqIsPendingTest, BadTarget) {
bool is_pending;
EXPECT_EQ(dif_rv_plic_software_irq_is_pending(
&plic_, RV_PLIC_PARAM_NUM_TARGET, &is_pending),
- kDifRvPlicBadArg);
+ kDifBadArg);
}
TEST_F(SoftwareIrqIsPendingTest, Target0Success) {
@@ -382,7 +372,7 @@
EXPECT_READ32(RV_PLIC_MSIP0_REG_OFFSET, 1);
EXPECT_EQ(dif_rv_plic_software_irq_is_pending(&plic_, kTarget0, &is_pending),
- kDifRvPlicOk);
+ kDifOk);
EXPECT_TRUE(is_pending);
// Cleared
@@ -390,7 +380,7 @@
EXPECT_READ32(RV_PLIC_MSIP0_REG_OFFSET, 0);
EXPECT_EQ(dif_rv_plic_software_irq_is_pending(&plic_, kTarget0, &is_pending),
- kDifRvPlicOk);
+ kDifOk);
EXPECT_FALSE(is_pending);
}
diff --git a/sw/device/lib/dif/meson.build b/sw/device/lib/dif/meson.build
index 7d2ff13..610bc57 100644
--- a/sw/device/lib/dif/meson.build
+++ b/sw/device/lib/dif/meson.build
@@ -153,6 +153,7 @@
dependencies: [
sw_lib_mmio,
sw_lib_bitfield,
+ sw_lib_dif_autogen_rv_plic,
],
)
)
@@ -160,9 +161,11 @@
test('dif_rv_plic_unittest', executable(
'dif_rv_plic_unittest',
sources: [
- hw_top_earlgrey_rv_plic_reg_h,
- meson.source_root() / 'sw/device/lib/dif/dif_rv_plic.c',
'dif_rv_plic_unittest.cc',
+ 'autogen/dif_rv_plic_autogen_unittest.cc',
+ meson.source_root() / 'sw/device/lib/dif/dif_rv_plic.c',
+ meson.source_root() / 'sw/device/lib/dif/autogen/dif_rv_plic_autogen.c',
+ hw_top_earlgrey_rv_plic_reg_h,
],
dependencies: [
sw_vendor_gtest,
diff --git a/sw/device/lib/testing/rv_plic_testutils.c b/sw/device/lib/testing/rv_plic_testutils.c
index 77b6385..4779828 100644
--- a/sw/device/lib/testing/rv_plic_testutils.c
+++ b/sw/device/lib/testing/rv_plic_testutils.c
@@ -4,6 +4,7 @@
#include "sw/device/lib/testing/rv_plic_testutils.h"
+#include "sw/device/lib/dif/dif_base.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/testing/check.h"
@@ -17,10 +18,10 @@
++irq_id) {
uint32_t priority = rand_testutils_gen32_range(kDifRvPlicMinPriority + 1,
kDifRvPlicMaxPriority);
- CHECK(dif_rv_plic_irq_set_priority(plic, irq_id, priority) == kDifRvPlicOk);
- CHECK(dif_rv_plic_irq_set_enabled(plic, irq_id, target,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk);
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(plic, irq_id, priority));
+ CHECK_DIF_OK(
+ dif_rv_plic_irq_set_enabled(plic, irq_id, target, kDifToggleEnabled));
}
- CHECK(dif_rv_plic_target_set_threshold(plic, target, kDifRvPlicMinPriority) ==
- kDifRvPlicOk);
+ CHECK_DIF_OK(
+ dif_rv_plic_target_set_threshold(plic, target, kDifRvPlicMinPriority));
}
diff --git a/sw/device/tests/autogen/plic_all_irqs_test.c b/sw/device/tests/autogen/plic_all_irqs_test.c
index 8eb9a3f..1a88f01 100644
--- a/sw/device/tests/autogen/plic_all_irqs_test.c
+++ b/sw/device/tests/autogen/plic_all_irqs_test.c
@@ -144,7 +144,7 @@
void handler_irq_external(void) {
// Find which interrupt fired at PLIC by claiming it.
dif_rv_plic_irq_id_t plic_irq_id;
- CHECK(dif_rv_plic_irq_claim(&plic, kHart, &plic_irq_id) == kDifRvPlicOk);
+ CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic, kHart, &plic_irq_id));
// Check if it is the right peripheral.
top_earlgrey_plic_peripheral_t peripheral = (top_earlgrey_plic_peripheral_t)
@@ -251,7 +251,7 @@
}
// Complete the IRQ at PLIC.
- CHECK(dif_rv_plic_irq_complete(&plic, kHart, plic_irq_id) == kDifRvPlicOk);
+ CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic, kHart, plic_irq_id));
}
/**
@@ -300,8 +300,7 @@
mmio_region_t base_addr =
mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR);
- CHECK(dif_rv_plic_init((dif_rv_plic_params_t){.base_addr = base_addr},
- &plic) == kDifRvPlicOk);
+ CHECK_DIF_OK(dif_rv_plic_init(base_addr, &plic));
}
/**
diff --git a/sw/device/tests/rv_plic_smoketest.c b/sw/device/tests/rv_plic_smoketest.c
index a1c90ce..c8f2dfe 100644
--- a/sw/device/tests/rv_plic_smoketest.c
+++ b/sw/device/tests/rv_plic_smoketest.c
@@ -72,9 +72,7 @@
void handler_irq_external(void) {
// Claim the IRQ by reading the Ibex specific CC register.
dif_rv_plic_irq_id_t interrupt_id;
- CHECK(
- dif_rv_plic_irq_claim(&plic0, kPlicTarget, &interrupt_id) == kDifRvPlicOk,
- "ISR is not implemented!");
+ CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic0, kPlicTarget, &interrupt_id));
// Check if the interrupted peripheral is UART.
top_earlgrey_plic_peripheral_t peripheral_id =
@@ -85,9 +83,7 @@
// Complete the IRQ by writing the IRQ source to the Ibex specific CC
// register.
- CHECK(dif_rv_plic_irq_complete(&plic0, kPlicTarget, interrupt_id) ==
- kDifRvPlicOk,
- "Unable to complete the IRQ request!");
+ CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic0, kPlicTarget, interrupt_id));
}
static void uart_initialise(mmio_region_t base_addr, dif_uart_t *uart) {
@@ -101,12 +97,6 @@
}));
}
-static void plic_initialise(mmio_region_t base_addr, dif_rv_plic_t *plic) {
- CHECK(dif_rv_plic_init((dif_rv_plic_params_t){.base_addr = base_addr},
- plic) == kDifRvPlicOk,
- "PLIC init failed!");
-}
-
/**
* Configures all the relevant interrupts in UART.
*/
@@ -122,29 +112,23 @@
*/
static void plic_configure_irqs(dif_rv_plic_t *plic) {
// Set IRQ priorities to MAX
- CHECK(dif_rv_plic_irq_set_priority(plic, kTopEarlgreyPlicIrqIdUart0RxOverflow,
- kDifRvPlicMaxPriority) == kDifRvPlicOk,
- "priority set for RX overflow failed!");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopEarlgreyPlicIrqIdUart0RxOverflow, kDifRvPlicMaxPriority));
- CHECK(dif_rv_plic_irq_set_priority(plic, kTopEarlgreyPlicIrqIdUart0TxEmpty,
- kDifRvPlicMaxPriority) == kDifRvPlicOk,
- "priority set for TX empty failed!");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopEarlgreyPlicIrqIdUart0TxEmpty, kDifRvPlicMaxPriority));
// Set Ibex IRQ priority threshold level
- CHECK(dif_rv_plic_target_set_threshold(&plic0, kPlicTarget,
- kDifRvPlicMinPriority) == kDifRvPlicOk,
- "threshold set failed!");
+ CHECK_DIF_OK(dif_rv_plic_target_set_threshold(&plic0, kPlicTarget,
+ kDifRvPlicMinPriority));
// Enable IRQs in PLIC
- CHECK(dif_rv_plic_irq_set_enabled(plic, kTopEarlgreyPlicIrqIdUart0RxOverflow,
- kPlicTarget,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "interrupt Enable for RX overflow failed!");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic,
+ kTopEarlgreyPlicIrqIdUart0RxOverflow,
+ kPlicTarget, kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic, kTopEarlgreyPlicIrqIdUart0TxEmpty,
- kPlicTarget,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "interrupt Enable for TX empty failed!");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopEarlgreyPlicIrqIdUart0TxEmpty, kPlicTarget, kDifToggleEnabled));
}
static void execute_test(dif_uart_t *uart) {
@@ -183,7 +167,7 @@
mmio_region_t plic_base_addr =
mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR);
- plic_initialise(plic_base_addr, &plic0);
+ CHECK_DIF_OK(dif_rv_plic_init(plic_base_addr, &plic0));
uart_configure_irqs(&uart0);
plic_configure_irqs(&plic0);
diff --git a/sw/device/tests/sim_dv/gpio_test.c b/sw/device/tests/sim_dv/gpio_test.c
index cdc23b8..f1f4487 100644
--- a/sw/device/tests/sim_dv/gpio_test.c
+++ b/sw/device/tests/sim_dv/gpio_test.c
@@ -68,28 +68,22 @@
static void plic_init_with_irqs(mmio_region_t base_addr, dif_rv_plic_t *plic) {
LOG_INFO("Initializing the PLIC.");
- CHECK(dif_rv_plic_init((dif_rv_plic_params_t){.base_addr = base_addr},
- plic) == kDifRvPlicOk,
- "dif_rv_plic_init failed");
+ CHECK_DIF_OK(dif_rv_plic_init(base_addr, plic));
for (uint32_t i = 0; i < kNumGpios; ++i) {
dif_rv_plic_irq_id_t plic_irq_id = i + kTopEarlgreyPlicIrqIdGpioGpio0;
// Set the priority of GPIO interrupts at PLIC to be >=1
- CHECK(dif_rv_plic_irq_set_priority(plic, plic_irq_id, 0x1) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(plic, plic_irq_id, 0x1));
// Enable all GPIO interrupts at the PLIC.
- CHECK(dif_rv_plic_irq_set_enabled(plic, plic_irq_id,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, plic_irq_id, kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
}
// Set the threshold for the Ibex to 0.
- CHECK(dif_rv_plic_target_set_threshold(plic, kTopEarlgreyPlicTargetIbex0,
- 0x0) == kDifRvPlicOk,
- "dif_rv_plic_target_set_threshold failed");
+ CHECK_DIF_OK(
+ dif_rv_plic_target_set_threshold(plic, kTopEarlgreyPlicTargetIbex0, 0x0));
}
/**
@@ -206,9 +200,8 @@
void handler_irq_external(void) {
// Find which interrupt fired at PLIC by claiming it.
dif_rv_plic_irq_id_t plic_irq_id;
- CHECK(dif_rv_plic_irq_claim(&plic, kTopEarlgreyPlicTargetIbex0,
- &plic_irq_id) == kDifRvPlicOk,
- "dif_rv_plic_irq_claim failed");
+ CHECK_DIF_OK(
+ dif_rv_plic_irq_claim(&plic, kTopEarlgreyPlicTargetIbex0, &plic_irq_id));
// Check if it is the right peripheral.
top_earlgrey_plic_peripheral_t peripheral = (top_earlgrey_plic_peripheral_t)
@@ -244,9 +237,8 @@
CHECK_DIF_OK(dif_gpio_irq_acknowledge(&gpio, gpio_pin_irq_fired));
// Complete the IRQ at PLIC.
- CHECK(dif_rv_plic_irq_complete(&plic, kTopEarlgreyPlicTargetIbex0,
- plic_irq_id) == kDifRvPlicOk,
- "dif_rv_plic_irq_complete failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic, kTopEarlgreyPlicTargetIbex0,
+ plic_irq_id));
}
const test_config_t kTestConfig;
@@ -260,9 +252,8 @@
dif_gpio_init(mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), &gpio));
// Initialize the PLIC.
- mmio_region_t plic_base_addr =
- mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR);
- plic_init_with_irqs(plic_base_addr, &plic);
+ plic_init_with_irqs(mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR),
+ &plic);
// Enable the external IRQ at Ibex.
irq_global_ctrl(true);
diff --git a/sw/device/tests/sim_dv/spi_tx_rx_test.c b/sw/device/tests/sim_dv/spi_tx_rx_test.c
index c6c892f..23a14a7 100644
--- a/sw/device/tests/sim_dv/spi_tx_rx_test.c
+++ b/sw/device/tests/sim_dv/spi_tx_rx_test.c
@@ -70,9 +70,8 @@
void handler_irq_external(void) {
// Find which interrupt fired at PLIC by claiming it.
dif_rv_plic_irq_id_t plic_irq_id;
- CHECK(dif_rv_plic_irq_claim(&plic0, kTopEarlgreyPlicTargetIbex0,
- &plic_irq_id) == kDifRvPlicOk,
- "dif_rv_plic_irq_claim failed");
+ CHECK_DIF_OK(
+ dif_rv_plic_irq_claim(&plic0, kTopEarlgreyPlicTargetIbex0, &plic_irq_id));
// Check if it is the right peripheral.
top_earlgrey_plic_peripheral_t peripheral = (top_earlgrey_plic_peripheral_t)
@@ -126,9 +125,8 @@
CHECK_DIF_OK(dif_spi_device_irq_acknowledge(&spi_device, spi_device_irq));
// Complete the IRQ at PLIC.
- CHECK(dif_rv_plic_irq_complete(&plic0, kTopEarlgreyPlicTargetIbex0,
- plic_irq_id) == kDifRvPlicOk,
- "dif_rv_plic_irq_complete failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic0, kTopEarlgreyPlicTargetIbex0,
+ plic_irq_id));
}
/**
@@ -167,74 +165,50 @@
static void plic_init_with_irqs(mmio_region_t base_addr, dif_rv_plic_t *plic) {
LOG_INFO("Initializing the PLIC.");
- CHECK(dif_rv_plic_init((dif_rv_plic_params_t){.base_addr = base_addr},
- plic) == kDifRvPlicOk,
- "dif_rv_plic_init failed");
+ CHECK_DIF_OK(dif_rv_plic_init(base_addr, plic));
// Set the priority of SPI DEVICE interrupts at PLIC to be >=1 (so ensure the
// target does get interrupted).
- CHECK(dif_rv_plic_irq_set_priority(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxFull,
- kDifRvPlicMaxPriority) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark,
- kDifRvPlicMaxPriority) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark,
- kDifRvPlicMaxPriority) == kDifRvPlicOk,
- , "dif_rv_plic_irq_set_priority failed");
- CHECK(
- dif_rv_plic_irq_set_priority(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxError,
- kDifRvPlicMaxPriority) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow,
- kDifRvPlicMaxPriority) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow,
- kDifRvPlicMaxPriority) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceRxFull, kDifRvPlicMaxPriority));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark, kDifRvPlicMaxPriority));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark, kDifRvPlicMaxPriority));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceRxError, kDifRvPlicMaxPriority));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow, kDifRvPlicMaxPriority));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow, kDifRvPlicMaxPriority));
// Set the threshold for the Ibex to 0.
- CHECK(dif_rv_plic_target_set_threshold(plic, kTopEarlgreyPlicTargetIbex0,
- 0x0) == kDifRvPlicOk,
- "dif_rv_plic_target_set_threshold failed");
+ CHECK_DIF_OK(
+ dif_rv_plic_target_set_threshold(plic, kTopEarlgreyPlicTargetIbex0, 0x0));
- CHECK(dif_rv_plic_irq_set_enabled(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxFull,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceRxFull, kTopEarlgreyPlicTargetIbex0,
+ kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark,
+ kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark,
+ kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxError,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceRxError, kTopEarlgreyPlicTargetIbex0,
+ kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow,
+ kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow,
+ kTopEarlgreyPlicTargetIbex0, kDifToggleEnabled));
}
static bool exp_irqs_fired(void) {
diff --git a/sw/device/tests/sim_dv/uart_tx_rx_test.c b/sw/device/tests/sim_dv/uart_tx_rx_test.c
index cc077ae..1227df3 100644
--- a/sw/device/tests/sim_dv/uart_tx_rx_test.c
+++ b/sw/device/tests/sim_dv/uart_tx_rx_test.c
@@ -4,6 +4,7 @@
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_base.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/handler.h"
@@ -221,9 +222,8 @@
void handler_irq_external(void) {
// Find which interrupt fired at PLIC by claiming it.
dif_rv_plic_irq_id_t plic_irq_id;
- CHECK(dif_rv_plic_irq_claim(&plic, kTopEarlgreyPlicTargetIbex0,
- &plic_irq_id) == kDifRvPlicOk,
- "dif_rv_plic_irq_claim failed");
+ CHECK_DIF_OK(
+ dif_rv_plic_irq_claim(&plic, kTopEarlgreyPlicTargetIbex0, &plic_irq_id));
// Check if it is the right peripheral.
top_earlgrey_plic_peripheral_t peripheral = (top_earlgrey_plic_peripheral_t)
@@ -267,9 +267,8 @@
CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart, uart_irq));
// Complete the IRQ at PLIC.
- CHECK(dif_rv_plic_irq_complete(&plic, kTopEarlgreyPlicTargetIbex0,
- plic_irq_id) == kDifRvPlicOk,
- "dif_rv_plic_irq_complete failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic, kTopEarlgreyPlicTargetIbex0,
+ plic_irq_id));
}
/**
@@ -308,82 +307,61 @@
static void plic_init_with_irqs(mmio_region_t base_addr, dif_rv_plic_t *plic) {
LOG_INFO("Initializing the PLIC. %0x", uart_irq_tx_watermartk_id);
- CHECK(dif_rv_plic_init((dif_rv_plic_params_t){.base_addr = base_addr},
- plic) == kDifRvPlicOk,
- "dif_rv_plic_init failed");
+ CHECK_DIF_OK(dif_rv_plic_init(base_addr, plic));
// Set the priority of UART interrupts at PLIC to be >=1 (so ensure the target
// does get interrupted).
- CHECK(dif_rv_plic_irq_set_priority(plic, uart_irq_tx_watermartk_id, 0x1) ==
- kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic, uart_irq_rx_watermartk_id, 0x2) ==
- kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic, uart_irq_tx_empty_id, 0x3) ==
- kDifRvPlicOk,
- , "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic, uart_irq_rx_overflow_id, 0x1) ==
- kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic, uart_irq_rx_frame_err_id, 0x2) ==
- kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic, uart_irq_rx_break_err_id, 0x3) ==
- kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic, uart_irq_rx_timeout_id, 0x1) ==
- kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic, uart_irq_rx_parity_err_id, 0x2) ==
- kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
+ CHECK_DIF_OK(
+ dif_rv_plic_irq_set_priority(plic, uart_irq_tx_watermartk_id, 0x1));
+ CHECK_DIF_OK(
+ dif_rv_plic_irq_set_priority(plic, uart_irq_rx_watermartk_id, 0x2));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(plic, uart_irq_tx_empty_id, 0x3));
+ CHECK_DIF_OK(
+ dif_rv_plic_irq_set_priority(plic, uart_irq_rx_overflow_id, 0x1));
+ CHECK_DIF_OK(
+ dif_rv_plic_irq_set_priority(plic, uart_irq_rx_frame_err_id, 0x2));
+ CHECK_DIF_OK(
+ dif_rv_plic_irq_set_priority(plic, uart_irq_rx_break_err_id, 0x3));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(plic, uart_irq_rx_timeout_id, 0x1));
+ CHECK_DIF_OK(
+ dif_rv_plic_irq_set_priority(plic, uart_irq_rx_parity_err_id, 0x2));
// Set the threshold for the Ibex to 0.
- CHECK(dif_rv_plic_target_set_threshold(plic, kTopEarlgreyPlicTargetIbex0,
- 0x0) == kDifRvPlicOk,
- "dif_rv_plic_target_set_threshold failed");
+ CHECK_DIF_OK(
+ dif_rv_plic_target_set_threshold(plic, kTopEarlgreyPlicTargetIbex0, 0x0));
// Enable all UART interrupts at the PLIC.
- CHECK(dif_rv_plic_irq_set_enabled(plic, uart_irq_tx_watermartk_id,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, uart_irq_tx_watermartk_id,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_watermartk_id,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_watermartk_id,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic, uart_irq_tx_empty_id,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, uart_irq_tx_empty_id,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_overflow_id,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_overflow_id,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_frame_err_id,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_frame_err_id,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_break_err_id,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_break_err_id,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_timeout_id,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_timeout_id,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifToggleEnabled));
- CHECK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_parity_err_id,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, uart_irq_rx_parity_err_id,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifToggleEnabled));
}
/**
diff --git a/util/topgen/templates/plic_all_irqs_test.c.tpl b/util/topgen/templates/plic_all_irqs_test.c.tpl
index 399fbc9..98e8975 100644
--- a/util/topgen/templates/plic_all_irqs_test.c.tpl
+++ b/util/topgen/templates/plic_all_irqs_test.c.tpl
@@ -68,7 +68,7 @@
void handler_irq_external(void) {
// Find which interrupt fired at PLIC by claiming it.
dif_rv_plic_irq_id_t plic_irq_id;
- CHECK(dif_rv_plic_irq_claim(&plic, kHart, &plic_irq_id) == kDifRvPlicOk);
+ CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic, kHart, &plic_irq_id));
// Check if it is the right peripheral.
top_earlgrey_plic_peripheral_t peripheral = (top_earlgrey_plic_peripheral_t)
@@ -89,7 +89,7 @@
}
// Complete the IRQ at PLIC.
- CHECK(dif_rv_plic_irq_complete(&plic, kHart, plic_irq_id) == kDifRvPlicOk);
+ CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic, kHart, plic_irq_id));
}
/**
@@ -110,8 +110,7 @@
mmio_region_t base_addr =
mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR);
- CHECK(dif_rv_plic_init((dif_rv_plic_params_t){.base_addr = base_addr},
- &plic) == kDifRvPlicOk);
+ CHECK_DIF_OK(dif_rv_plic_init(base_addr, &plic));
}
/**
