commit a758451dcce46c544a3c6db45ba5c85abdda5313
author Weicai Yang <weicai@google.com> Thu Jun 04 16:58:27 2020 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Mon Jun 08 17:14:32 2020 -0700
tree 87c13cdb68386133a35d421031e6e1df76126ac2
parent ec0cb45a677eea4f56c26019db97b4fa853937e5

[dv/xbar] Fix xcelium compile error

1. Fix error #2404, xcelium doesn't allow to force one of var in packed
struct
2. Also change to only drive clocks used by xbar

Signed-off-by: Weicai Yang <weicai@google.com>

hw/top_earlgrey/data/tb__xbar_connect.sv.tpl

diff --git a/hw/top_earlgrey/data/tb__xbar_connect.sv.tpl b/hw/top_earlgrey/data/tb__xbar_connect.sv.tpl
index 76ccb26..8072fa0 100644
--- a/hw/top_earlgrey/data/tb__xbar_connect.sv.tpl
+++ b/hw/top_earlgrey/data/tb__xbar_connect.sv.tpl
@@ -9,23 +9,24 @@
 top_hier = 'tb.dut.top_' + top["name"] + '.'
 clk_hier = top_hier + top["clocks"]["hier_paths"]["top"]
 
-clk_freq = {}
-for clock in top["clocks"]["srcs"]:
-  clk_freq[clock["name"]] = clock["freq"]
-
 clk_src = {}
 for xbar in top["xbar"]:
   for clk, src in xbar["clock_srcs"].items():
-    clk_src[clk] = "clk_" + src
+    clk_src[clk] = src
+
+clk_freq = {}
+for clock in top["clocks"]["srcs"]:
+  if clock["name"] in clk_src.values():
+    clk_freq[clock["name"]] = clock["freq"]
 
 hosts = {}
 devices = {}
 for xbar in top["xbar"]:
   for node in xbar["nodes"]:
     if node["type"] == "host" and not node["xbar"]:
-      hosts[node["name"]] = clk_src[node["clock"]]
+      hosts[node["name"]] = "clk_" + clk_src[node["clock"]]
     elif node["type"] == "device" and not node["xbar"]:
-      devices[node["name"]] = clk_src[node["clock"]]
+      devices[node["name"]] = "clk_" + clk_src[node["clock"]]
 %>\
 % for c in clk_freq.keys():
 wire clk_${c};
@@ -56,11 +57,9 @@
 % endfor
 
     // bypass clkmgr, force clocks directly
-% for grp in top["clocks"]["groups"]:
-  % for name, src in grp["clocks"].items():
-    % if grp["src"] == "top":
-    force ${clk_hier}${name} = clk_${src};
-    % endif
+% for xbar in top["xbar"]:
+  % for clk, src in xbar["clock_srcs"].items():
+    force ${top_hier}u_xbar_${xbar["name"]}.${clk} = clk_${src};
   % endfor
 % endfor
 

hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv

diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
index bb439ff..af13863 100644
--- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -7,10 +7,6 @@
 clk_rst_if clk_rst_if_main(.clk(clk_main), .rst_n(rst_n));
 wire clk_io;
 clk_rst_if clk_rst_if_io(.clk(clk_io), .rst_n(rst_n));
-wire clk_usb;
-clk_rst_if clk_rst_if_usb(.clk(clk_usb), .rst_n(rst_n));
-wire clk_aon;
-clk_rst_if clk_rst_if_aon(.clk(clk_aon), .rst_n(rst_n));
 
 tl_if corei_tl_if(clk_main, rst_n);
 tl_if cored_tl_if(clk_main, rst_n);
@@ -50,21 +46,11 @@
     clk_rst_if_main.set_freq_mhz(100000000 / 1000_000.0);
     clk_rst_if_io.set_active(.drive_rst_n_val(0));
     clk_rst_if_io.set_freq_mhz(100000000 / 1000_000.0);
-    clk_rst_if_usb.set_active(.drive_rst_n_val(0));
-    clk_rst_if_usb.set_freq_mhz(48000000 / 1000_000.0);
-    clk_rst_if_aon.set_active(.drive_rst_n_val(0));
-    clk_rst_if_aon.set_freq_mhz(200000 / 1000_000.0);
 
     // bypass clkmgr, force clocks directly
-    force tb.dut.top_earlgrey.clkmgr_clocks.clk_main_aes = clk_main;
-    force tb.dut.top_earlgrey.clkmgr_clocks.clk_main_hmac = clk_main;
-    force tb.dut.top_earlgrey.clkmgr_clocks.clk_main_infra = clk_main;
-    force tb.dut.top_earlgrey.clkmgr_clocks.clk_io_infra = clk_io;
-    force tb.dut.top_earlgrey.clkmgr_clocks.clk_io_secure = clk_io;
-    force tb.dut.top_earlgrey.clkmgr_clocks.clk_main_secure = clk_main;
-    force tb.dut.top_earlgrey.clkmgr_clocks.clk_io_peri = clk_io;
-    force tb.dut.top_earlgrey.clkmgr_clocks.clk_usb_peri = clk_usb;
-    force tb.dut.top_earlgrey.clkmgr_clocks.clk_io_timers = clk_io;
+    force tb.dut.top_earlgrey.u_xbar_main.clk_main_i = clk_main;
+    force tb.dut.top_earlgrey.u_xbar_main.clk_fixed_i = clk_io;
+    force tb.dut.top_earlgrey.u_xbar_peri.clk_peri_i = clk_io;
 
     // bypass rstmgr, force resets directly
     force tb.dut.top_earlgrey.u_xbar_main.rst_main_ni = rst_n;