commit a6b5a1e33f5164f45812839f4f32430ee2a60c26
author Timothy Chen <timothytim@google.com> Mon Apr 12 14:20:30 2021 -0700
committer tjaychen <timothytim@google.com> Mon Apr 12 17:13:03 2021 -0700
tree dcbe3d5f52e6db34461ec6732d02c80e47d1b594
parent 2a1cf3e7234a1e95775b81e5fdfb304af8dacb75

[top] Turn on secure ibex for asic

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv

diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
index 2bcf6b1..9fbb548 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
@@ -831,6 +831,7 @@
     .RomCtrlBootRomInitFile(BootRomInitFile),
     .IbexRegFile(ibex_pkg::RegFileFPGA),
     .IbexPipeLine(1),
+    .SecureIbex(0),
     .SramCtrlRetAonInstrExec(0),
     .SramCtrlMainInstrExec(1),
     .PinmuxAonTargetCfg(PinmuxTargetCfg)

hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 2cff1ba..50f4723 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -29,7 +29,8 @@
   // Manually defined parameters
   parameter ibex_pkg::regfile_e IbexRegFile = ibex_pkg::RegFileFF,
   parameter bit IbexICache = 1,
-  parameter bit IbexPipeLine = 0
+  parameter bit IbexPipeLine = 0,
+  parameter bit SecureIbex = 1
 ) (
   // Reset, clocks defined as part of intermodule
   input               rst_ni,
@@ -718,7 +719,7 @@
     .ICacheECC                (1),
     .BranchPredictor          (0),
     .DbgTriggerEn             (1),
-    .SecureIbex               (0),
+    .SecureIbex               (SecureIbex),
     .DmHaltAddr               (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress[31:0]),
     .DmExceptionAddr          (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress[31:0]),
     .PipeLine                 (IbexPipeLine)

util/topgen/templates/chiplevel.sv.tpl

diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index 15d6ccd..93cb79e 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -1108,6 +1108,7 @@
 % endif
     .IbexRegFile(ibex_pkg::RegFileFPGA),
     .IbexPipeLine(1),
+    .SecureIbex(0),
     .SramCtrlRetAonInstrExec(0),
     .SramCtrlMainInstrExec(1),
     .PinmuxAonTargetCfg(PinmuxTargetCfg)

util/topgen/templates/toplevel.sv.tpl

diff --git a/util/topgen/templates/toplevel.sv.tpl b/util/topgen/templates/toplevel.sv.tpl
index c9def1c..444592e 100644
--- a/util/topgen/templates/toplevel.sv.tpl
+++ b/util/topgen/templates/toplevel.sv.tpl
@@ -58,7 +58,8 @@
 % endif
   parameter ibex_pkg::regfile_e IbexRegFile = ibex_pkg::RegFileFF,
   parameter bit IbexICache = 1,
-  parameter bit IbexPipeLine = 0
+  parameter bit IbexPipeLine = 0,
+  parameter bit SecureIbex = 1
 ) (
   // Reset, clocks defined as part of intermodule
   input               rst_ni,
@@ -270,7 +271,7 @@
     .ICacheECC                (1),
     .BranchPredictor          (0),
     .DbgTriggerEn             (1),
-    .SecureIbex               (0),
+    .SecureIbex               (SecureIbex),
     .DmHaltAddr               (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress[31:0]),
     .DmExceptionAddr          (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress[31:0]),
     .PipeLine                 (IbexPipeLine)