commit a6833b1d7165b5543f6bce7d023f305b384cd48f
author Timothy Chen <timothytim@google.com> Wed Mar 03 14:58:38 2021 -0800
committer tjaychen <timothytim@google.com> Wed Mar 03 18:33:28 2021 -0800
tree 5b9fddfc4ae6ee632659b7f744fb221993145475
parent a6f582993cf4368aab54cf865341deeff9115003

[top] Correct memory connection bit widths

This solution is not complete, please see #5446

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/top_earlgrey/data/top_earlgrey.sv.tpl

diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index fb27a26..92fc843 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -363,8 +363,8 @@
   logic ${lib.bitarray(1,          max_char)} ${m["name"]}_gnt;
   logic ${lib.bitarray(1,          max_char)} ${m["name"]}_we;
   logic ${lib.bitarray(addr_width, max_char)} ${m["name"]}_addr;
-  logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_wdata;
-  logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_wmask;
+  logic ${lib.bitarray(data_width, max_char)} ${m["name"]}_wdata;
+  logic ${lib.bitarray(data_width, max_char)} ${m["name"]}_wmask;
   logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_rdata;
   logic ${lib.bitarray(1,          max_char)} ${m["name"]}_rvalid;
   logic ${lib.bitarray(2,          max_char)} ${m["name"]}_rerror;

hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index e80df10..b6fd2b7 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -771,8 +771,8 @@
   logic        ram_main_gnt;
   logic        ram_main_we;
   logic [14:0] ram_main_addr;
-  logic [38:0] ram_main_wdata;
-  logic [38:0] ram_main_wmask;
+  logic [31:0] ram_main_wdata;
+  logic [31:0] ram_main_wmask;
   logic [38:0] ram_main_rdata;
   logic        ram_main_rvalid;
   logic [1:0]  ram_main_rerror;
@@ -831,8 +831,8 @@
   logic        ram_ret_aon_gnt;
   logic        ram_ret_aon_we;
   logic [9:0] ram_ret_aon_addr;
-  logic [38:0] ram_ret_aon_wdata;
-  logic [38:0] ram_ret_aon_wmask;
+  logic [31:0] ram_ret_aon_wdata;
+  logic [31:0] ram_ret_aon_wmask;
   logic [38:0] ram_ret_aon_rdata;
   logic        ram_ret_aon_rvalid;
   logic [1:0]  ram_ret_aon_rerror;