[rtl] Generate reg-tops for "mem" interface on flash_ctrl
These are auto-generated files that weren't checked in with c74ba0a
and (because of a bug in a CI script) we didn't spot them.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_mem_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_mem_reg_top.sv
new file mode 100644
index 0000000..9870270
--- /dev/null
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_mem_reg_top.sv
@@ -0,0 +1,99 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module flash_ctrl_mem_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import flash_ctrl_reg_pkg::* ;
+
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ logic intg_err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_q <= '0;
+ end else if (intg_err) begin
+ intg_err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = intg_err_q | intg_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ tlul_pkg::tl_h2d_t tl_socket_h2d [0];
+ tlul_pkg::tl_d2h_t tl_socket_d2h [0];
+
+ logic [0:0] reg_steer;
+
+ // socket_1n connection
+
+ // Create Socket_1n
+ tlul_socket_1n #(
+ .N (0),
+ .HReqPass (1'b1),
+ .HRspPass (1'b1),
+ .DReqPass ({0{1'b1}}),
+ .DRspPass ({0{1'b1}}),
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth ({0{4'h0}}),
+ .DRspDepth ({0{4'h0}})
+ ) u_socket (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tl_h_i (tl_i),
+ .tl_h_o (tl_o_pre),
+ .tl_d_o (tl_socket_h2d),
+ .tl_d_i (tl_socket_d2h),
+ .dev_select_i (reg_steer)
+ );
+
+ // Create steering logic
+ always_comb begin
+ reg_steer = -1; // Default set to register
+
+ // TODO: Can below codes be unique case () inside ?
+ if (intg_err) begin
+ reg_steer = -1;
+ end
+ end
+
+ // Unused signal tieoff
+ // devmode_i is not used if there are no registers
+ logic unused_devmode;
+ assign unused_devmode = ^devmode_i;
+endmodule
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_mem_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_mem_reg_top.sv
new file mode 100644
index 0000000..9870270
--- /dev/null
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_mem_reg_top.sv
@@ -0,0 +1,99 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module flash_ctrl_mem_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import flash_ctrl_reg_pkg::* ;
+
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ logic intg_err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_q <= '0;
+ end else if (intg_err) begin
+ intg_err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = intg_err_q | intg_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ tlul_pkg::tl_h2d_t tl_socket_h2d [0];
+ tlul_pkg::tl_d2h_t tl_socket_d2h [0];
+
+ logic [0:0] reg_steer;
+
+ // socket_1n connection
+
+ // Create Socket_1n
+ tlul_socket_1n #(
+ .N (0),
+ .HReqPass (1'b1),
+ .HRspPass (1'b1),
+ .DReqPass ({0{1'b1}}),
+ .DRspPass ({0{1'b1}}),
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth ({0{4'h0}}),
+ .DRspDepth ({0{4'h0}})
+ ) u_socket (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tl_h_i (tl_i),
+ .tl_h_o (tl_o_pre),
+ .tl_d_o (tl_socket_h2d),
+ .tl_d_i (tl_socket_d2h),
+ .dev_select_i (reg_steer)
+ );
+
+ // Create steering logic
+ always_comb begin
+ reg_steer = -1; // Default set to register
+
+ // TODO: Can below codes be unique case () inside ?
+ if (intg_err) begin
+ reg_steer = -1;
+ end
+ end
+
+ // Unused signal tieoff
+ // devmode_i is not used if there are no registers
+ logic unused_devmode;
+ assign unused_devmode = ^devmode_i;
+endmodule
