| commit | 25468b4a8a6b3dc53f87a0ccdfb7fde34c1ef657 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Thu Mar 11 15:20:10 2021 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Tue Mar 16 13:10:35 2021 +0000 |
| tree | 0e6b4a1cb56b878d188f9772beecb62aa8064875 | |
| parent | 9b819fbff4d6f92a440b4c8e075d6fc25d7316f7 [diff] |
[dv] Get blocks with multiple device interfaces working with chip DV The big change here is that we might now generate several *_ral_pkg.sv files for a block: one per device interface. To support this, gen_dv.py now has a loop over device interfaces (just like gen_rtl.py and gen_fpv.py). What's more, we have the same problem as gen_fpv where we need to list the generated files in the core file properly. To get that right, we pull core file generation out of ralgen.py and put it into gen_fpv, where we know what files we've created. Finally (and this is the biggest part of the patch), we split up the top-level and block-level versions of uvm_reg.sv.tpl. The top-level and block-level templates share functions from uvm_reg_base.sv.tpl, and I think the result is a bit easier to follow. There's also a liberal sprinking of big "##"-style comments to try to make the template code a bit easier to follow. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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