[keymgr] Actually increase salt / sw binding sizes
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/keymgr/data/keymgr.hjson b/hw/ip/keymgr/data/keymgr.hjson
index d819842..e6647cc 100644
--- a/hw/ip/keymgr/data/keymgr.hjson
+++ b/hw/ip/keymgr/data/keymgr.hjson
@@ -180,13 +180,13 @@
{ name: "NumSaltReg",
desc: "Number of Registers for SW inputs (Salt)",
type: "int",
- default: "4",
+ default: "8",
local: "true"
},
{ name: "NumSwBindingReg",
desc: "Number of Registers for SW inputs (SW binding)",
type: "int",
- default: "4",
+ default: "8",
local: "true"
},
{ name: "NumOutReg",
diff --git a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
index 6bdc473..e155362 100644
--- a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
+++ b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
@@ -21,20 +21,20 @@
typedef struct packed {
// some portions are unused, which are 0s
- bit [keymgr_pkg::AdvDataWidth-keymgr_pkg::KeyWidth-TL_DW*4-1:0] unused;
- bit [3:0][TL_DW-1:0] SoftwareBinding;
+ bit [keymgr_pkg::AdvDataWidth-keymgr_pkg::KeyWidth-keymgr_pkg::SwBindingWidth-1:0] unused;
+ bit [keymgr_reg_pkg::NumSwBindingReg-1:0][TL_DW-1:0] SoftwareBinding;
bit [keymgr_pkg::KeyWidth-1:0] OwnerRootSecret;
} adv_owner_int_data_t;
typedef struct packed {
// some portions are unused, which are 0s
- bit [keymgr_pkg::AdvDataWidth-TL_DW*4-1:0] unused;
- bit [3:0][TL_DW-1:0] SoftwareBinding;
+ bit [keymgr_pkg::AdvDataWidth-keymgr_pkg::SwBindingWidth-1:0] unused;
+ bit [keymgr_reg_pkg::NumSwBindingReg-1:0][TL_DW-1:0] SoftwareBinding;
} adv_owner_data_t;
typedef struct packed {
bit [TL_DW-1:0] KeyVersion;
- bit [3:0][TL_DW-1:0] Salt;
+ bit [keymgr_reg_pkg::NumSaltReg-1:0][TL_DW-1:0] Salt;
keymgr_pkg::seed_t KeyID;
keymgr_pkg::seed_t SoftwareExportConstant;
} gen_out_data_t;
@@ -704,6 +704,10 @@
act = {<<8{byte_data_q}};
exp.OwnerRootSecret = cfg.keymgr_vif.flash.seeds[flash_ctrl_pkg::OwnerSeedIdx];
+ exp.SoftwareBinding[7] = `gmv(ral.sw_binding_7);
+ exp.SoftwareBinding[6] = `gmv(ral.sw_binding_6);
+ exp.SoftwareBinding[5] = `gmv(ral.sw_binding_5);
+ exp.SoftwareBinding[4] = `gmv(ral.sw_binding_4);
exp.SoftwareBinding[3] = `gmv(ral.sw_binding_3);
exp.SoftwareBinding[2] = `gmv(ral.sw_binding_2);
exp.SoftwareBinding[1] = `gmv(ral.sw_binding_1);
@@ -711,10 +715,9 @@
`CREATE_CMP_STR(unused)
`CREATE_CMP_STR(OwnerRootSecret)
- `CREATE_CMP_STR(SoftwareBinding[3])
- `CREATE_CMP_STR(SoftwareBinding[2])
- `CREATE_CMP_STR(SoftwareBinding[1])
- `CREATE_CMP_STR(SoftwareBinding[0])
+ for (int i=0; i < keymgr_reg_pkg::NumSwBindingReg; i++) begin
+ `CREATE_CMP_STR(SoftwareBinding[i])
+ end
if (exp_match) begin
`DV_CHECK_EQ(act, exp, str)
@@ -731,16 +734,19 @@
act = {<<8{byte_data_q}};
+ exp.SoftwareBinding[7] = `gmv(ral.sw_binding_7);
+ exp.SoftwareBinding[6] = `gmv(ral.sw_binding_6);
+ exp.SoftwareBinding[5] = `gmv(ral.sw_binding_5);
+ exp.SoftwareBinding[4] = `gmv(ral.sw_binding_4);
exp.SoftwareBinding[3] = `gmv(ral.sw_binding_3);
exp.SoftwareBinding[2] = `gmv(ral.sw_binding_2);
exp.SoftwareBinding[1] = `gmv(ral.sw_binding_1);
exp.SoftwareBinding[0] = `gmv(ral.sw_binding_0);
`CREATE_CMP_STR(unused)
- `CREATE_CMP_STR(SoftwareBinding[3])
- `CREATE_CMP_STR(SoftwareBinding[2])
- `CREATE_CMP_STR(SoftwareBinding[1])
- `CREATE_CMP_STR(SoftwareBinding[0])
+ for (int i=0; i < keymgr_reg_pkg::NumSwBindingReg; i++) begin
+ `CREATE_CMP_STR(SoftwareBinding[i])
+ end
`DV_CHECK_EQ(act, exp, str)
@@ -801,6 +807,10 @@
exp.Salt[1] = `gmv(ral.salt_1);
exp.Salt[2] = `gmv(ral.salt_2);
exp.Salt[3] = `gmv(ral.salt_3);
+ exp.Salt[4] = `gmv(ral.salt_4);
+ exp.Salt[5] = `gmv(ral.salt_5);
+ exp.Salt[6] = `gmv(ral.salt_6);
+ exp.Salt[7] = `gmv(ral.salt_7);
case (dest)
keymgr_pkg::Kmac: exp.KeyID = keymgr_pkg::RndCnstKmacSeedDefault;
keymgr_pkg::Hmac: exp.KeyID = keymgr_pkg::RndCnstHmacSeedDefault;
diff --git a/hw/ip/keymgr/rtl/keymgr_pkg.sv b/hw/ip/keymgr/rtl/keymgr_pkg.sv
index 7577e4a..58ce0a6 100644
--- a/hw/ip/keymgr/rtl/keymgr_pkg.sv
+++ b/hw/ip/keymgr/rtl/keymgr_pkg.sv
@@ -76,9 +76,10 @@
parameter int StageWidth = $clog2(KeyMgrStages);
// Max Payload Width to derivation function
- // This should be decomposed to 1600 - security_strength*2
// see security strength description https://keccak.team/keccak.html
- parameter int KDFMaxWidth = 1088;
+ // The max width here is chosen arbitrarily to ensure we do not get out of hand.
+ // Since KMAC is a MAC operation, the data can be as long as we need.
+ parameter int KDFMaxWidth = 1600;
// Enumeration for operations
typedef enum logic [2:0] {
diff --git a/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv b/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv
index 2146f9a..44383c7 100644
--- a/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv
+++ b/hw/ip/keymgr/rtl/keymgr_reg_pkg.sv
@@ -7,8 +7,8 @@
package keymgr_reg_pkg;
// Param list
- parameter int NumSaltReg = 4;
- parameter int NumSwBindingReg = 4;
+ parameter int NumSaltReg = 8;
+ parameter int NumSwBindingReg = 8;
parameter int NumOutReg = 8;
parameter int NumKeyVersion = 1;
parameter int NumAlerts = 2;
@@ -169,16 +169,16 @@
// Register -> HW type
typedef struct packed {
- keymgr_reg2hw_intr_state_reg_t intr_state; // [420:420]
- keymgr_reg2hw_intr_enable_reg_t intr_enable; // [419:419]
- keymgr_reg2hw_intr_test_reg_t intr_test; // [418:417]
- keymgr_reg2hw_alert_test_reg_t alert_test; // [416:413]
- keymgr_reg2hw_control_reg_t control; // [412:407]
- keymgr_reg2hw_sideload_clear_reg_t sideload_clear; // [406:406]
- keymgr_reg2hw_reseed_interval_reg_t reseed_interval; // [405:390]
- keymgr_reg2hw_sw_binding_regwen_reg_t sw_binding_regwen; // [389:388]
- keymgr_reg2hw_sw_binding_mreg_t [3:0] sw_binding; // [387:260]
- keymgr_reg2hw_salt_mreg_t [3:0] salt; // [259:132]
+ keymgr_reg2hw_intr_state_reg_t intr_state; // [676:676]
+ keymgr_reg2hw_intr_enable_reg_t intr_enable; // [675:675]
+ keymgr_reg2hw_intr_test_reg_t intr_test; // [674:673]
+ keymgr_reg2hw_alert_test_reg_t alert_test; // [672:669]
+ keymgr_reg2hw_control_reg_t control; // [668:663]
+ keymgr_reg2hw_sideload_clear_reg_t sideload_clear; // [662:662]
+ keymgr_reg2hw_reseed_interval_reg_t reseed_interval; // [661:646]
+ keymgr_reg2hw_sw_binding_regwen_reg_t sw_binding_regwen; // [645:644]
+ keymgr_reg2hw_sw_binding_mreg_t [7:0] sw_binding; // [643:388]
+ keymgr_reg2hw_salt_mreg_t [7:0] salt; // [387:132]
keymgr_reg2hw_key_version_mreg_t [0:0] key_version; // [131:100]
keymgr_reg2hw_max_creator_key_ver_reg_t max_creator_key_ver; // [99:68]
keymgr_reg2hw_max_owner_int_key_ver_reg_t max_owner_int_key_ver; // [67:36]
@@ -213,36 +213,44 @@
parameter logic [BlockAw-1:0] KEYMGR_SW_BINDING_1_OFFSET = 8'h 28;
parameter logic [BlockAw-1:0] KEYMGR_SW_BINDING_2_OFFSET = 8'h 2c;
parameter logic [BlockAw-1:0] KEYMGR_SW_BINDING_3_OFFSET = 8'h 30;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_0_OFFSET = 8'h 34;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_1_OFFSET = 8'h 38;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_2_OFFSET = 8'h 3c;
- parameter logic [BlockAw-1:0] KEYMGR_SALT_3_OFFSET = 8'h 40;
- parameter logic [BlockAw-1:0] KEYMGR_KEY_VERSION_OFFSET = 8'h 44;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET = 8'h 48;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_CREATOR_KEY_VER_OFFSET = 8'h 4c;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET = 8'h 50;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_INT_KEY_VER_OFFSET = 8'h 54;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET = 8'h 58;
- parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_KEY_VER_OFFSET = 8'h 5c;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET = 8'h 60;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET = 8'h 64;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET = 8'h 68;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET = 8'h 6c;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET = 8'h 70;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET = 8'h 74;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET = 8'h 78;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET = 8'h 7c;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET = 8'h 80;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET = 8'h 84;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET = 8'h 88;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET = 8'h 8c;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET = 8'h 90;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET = 8'h 94;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET = 8'h 98;
- parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET = 8'h 9c;
- parameter logic [BlockAw-1:0] KEYMGR_WORKING_STATE_OFFSET = 8'h a0;
- parameter logic [BlockAw-1:0] KEYMGR_OP_STATUS_OFFSET = 8'h a4;
- parameter logic [BlockAw-1:0] KEYMGR_ERR_CODE_OFFSET = 8'h a8;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_BINDING_4_OFFSET = 8'h 34;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_BINDING_5_OFFSET = 8'h 38;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_BINDING_6_OFFSET = 8'h 3c;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_BINDING_7_OFFSET = 8'h 40;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_0_OFFSET = 8'h 44;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_1_OFFSET = 8'h 48;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_2_OFFSET = 8'h 4c;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_3_OFFSET = 8'h 50;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_4_OFFSET = 8'h 54;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_5_OFFSET = 8'h 58;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_6_OFFSET = 8'h 5c;
+ parameter logic [BlockAw-1:0] KEYMGR_SALT_7_OFFSET = 8'h 60;
+ parameter logic [BlockAw-1:0] KEYMGR_KEY_VERSION_OFFSET = 8'h 64;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET = 8'h 68;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_CREATOR_KEY_VER_OFFSET = 8'h 6c;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET = 8'h 70;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_INT_KEY_VER_OFFSET = 8'h 74;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET = 8'h 78;
+ parameter logic [BlockAw-1:0] KEYMGR_MAX_OWNER_KEY_VER_OFFSET = 8'h 7c;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET = 8'h 80;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET = 8'h 84;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET = 8'h 88;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET = 8'h 8c;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET = 8'h 90;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET = 8'h 94;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET = 8'h 98;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET = 8'h 9c;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET = 8'h a0;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET = 8'h a4;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET = 8'h a8;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET = 8'h ac;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET = 8'h b0;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET = 8'h b4;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET = 8'h b8;
+ parameter logic [BlockAw-1:0] KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET = 8'h bc;
+ parameter logic [BlockAw-1:0] KEYMGR_WORKING_STATE_OFFSET = 8'h c0;
+ parameter logic [BlockAw-1:0] KEYMGR_OP_STATUS_OFFSET = 8'h c4;
+ parameter logic [BlockAw-1:0] KEYMGR_ERR_CODE_OFFSET = 8'h c8;
// Reset values for hwext registers and their fields
parameter logic [0:0] KEYMGR_INTR_TEST_RESVAL = 1'h 0;
@@ -270,10 +278,18 @@
KEYMGR_SW_BINDING_1,
KEYMGR_SW_BINDING_2,
KEYMGR_SW_BINDING_3,
+ KEYMGR_SW_BINDING_4,
+ KEYMGR_SW_BINDING_5,
+ KEYMGR_SW_BINDING_6,
+ KEYMGR_SW_BINDING_7,
KEYMGR_SALT_0,
KEYMGR_SALT_1,
KEYMGR_SALT_2,
KEYMGR_SALT_3,
+ KEYMGR_SALT_4,
+ KEYMGR_SALT_5,
+ KEYMGR_SALT_6,
+ KEYMGR_SALT_7,
KEYMGR_KEY_VERSION,
KEYMGR_MAX_CREATOR_KEY_VER_REGWEN,
KEYMGR_MAX_CREATOR_KEY_VER,
@@ -303,7 +319,7 @@
} keymgr_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] KEYMGR_PERMIT [43] = '{
+ parameter logic [3:0] KEYMGR_PERMIT [51] = '{
4'b 0001, // index[ 0] KEYMGR_INTR_STATE
4'b 0001, // index[ 1] KEYMGR_INTR_ENABLE
4'b 0001, // index[ 2] KEYMGR_INTR_TEST
@@ -317,36 +333,44 @@
4'b 1111, // index[10] KEYMGR_SW_BINDING_1
4'b 1111, // index[11] KEYMGR_SW_BINDING_2
4'b 1111, // index[12] KEYMGR_SW_BINDING_3
- 4'b 1111, // index[13] KEYMGR_SALT_0
- 4'b 1111, // index[14] KEYMGR_SALT_1
- 4'b 1111, // index[15] KEYMGR_SALT_2
- 4'b 1111, // index[16] KEYMGR_SALT_3
- 4'b 1111, // index[17] KEYMGR_KEY_VERSION
- 4'b 0001, // index[18] KEYMGR_MAX_CREATOR_KEY_VER_REGWEN
- 4'b 1111, // index[19] KEYMGR_MAX_CREATOR_KEY_VER
- 4'b 0001, // index[20] KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN
- 4'b 1111, // index[21] KEYMGR_MAX_OWNER_INT_KEY_VER
- 4'b 0001, // index[22] KEYMGR_MAX_OWNER_KEY_VER_REGWEN
- 4'b 1111, // index[23] KEYMGR_MAX_OWNER_KEY_VER
- 4'b 1111, // index[24] KEYMGR_SW_SHARE0_OUTPUT_0
- 4'b 1111, // index[25] KEYMGR_SW_SHARE0_OUTPUT_1
- 4'b 1111, // index[26] KEYMGR_SW_SHARE0_OUTPUT_2
- 4'b 1111, // index[27] KEYMGR_SW_SHARE0_OUTPUT_3
- 4'b 1111, // index[28] KEYMGR_SW_SHARE0_OUTPUT_4
- 4'b 1111, // index[29] KEYMGR_SW_SHARE0_OUTPUT_5
- 4'b 1111, // index[30] KEYMGR_SW_SHARE0_OUTPUT_6
- 4'b 1111, // index[31] KEYMGR_SW_SHARE0_OUTPUT_7
- 4'b 1111, // index[32] KEYMGR_SW_SHARE1_OUTPUT_0
- 4'b 1111, // index[33] KEYMGR_SW_SHARE1_OUTPUT_1
- 4'b 1111, // index[34] KEYMGR_SW_SHARE1_OUTPUT_2
- 4'b 1111, // index[35] KEYMGR_SW_SHARE1_OUTPUT_3
- 4'b 1111, // index[36] KEYMGR_SW_SHARE1_OUTPUT_4
- 4'b 1111, // index[37] KEYMGR_SW_SHARE1_OUTPUT_5
- 4'b 1111, // index[38] KEYMGR_SW_SHARE1_OUTPUT_6
- 4'b 1111, // index[39] KEYMGR_SW_SHARE1_OUTPUT_7
- 4'b 0001, // index[40] KEYMGR_WORKING_STATE
- 4'b 0001, // index[41] KEYMGR_OP_STATUS
- 4'b 0001 // index[42] KEYMGR_ERR_CODE
+ 4'b 1111, // index[13] KEYMGR_SW_BINDING_4
+ 4'b 1111, // index[14] KEYMGR_SW_BINDING_5
+ 4'b 1111, // index[15] KEYMGR_SW_BINDING_6
+ 4'b 1111, // index[16] KEYMGR_SW_BINDING_7
+ 4'b 1111, // index[17] KEYMGR_SALT_0
+ 4'b 1111, // index[18] KEYMGR_SALT_1
+ 4'b 1111, // index[19] KEYMGR_SALT_2
+ 4'b 1111, // index[20] KEYMGR_SALT_3
+ 4'b 1111, // index[21] KEYMGR_SALT_4
+ 4'b 1111, // index[22] KEYMGR_SALT_5
+ 4'b 1111, // index[23] KEYMGR_SALT_6
+ 4'b 1111, // index[24] KEYMGR_SALT_7
+ 4'b 1111, // index[25] KEYMGR_KEY_VERSION
+ 4'b 0001, // index[26] KEYMGR_MAX_CREATOR_KEY_VER_REGWEN
+ 4'b 1111, // index[27] KEYMGR_MAX_CREATOR_KEY_VER
+ 4'b 0001, // index[28] KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN
+ 4'b 1111, // index[29] KEYMGR_MAX_OWNER_INT_KEY_VER
+ 4'b 0001, // index[30] KEYMGR_MAX_OWNER_KEY_VER_REGWEN
+ 4'b 1111, // index[31] KEYMGR_MAX_OWNER_KEY_VER
+ 4'b 1111, // index[32] KEYMGR_SW_SHARE0_OUTPUT_0
+ 4'b 1111, // index[33] KEYMGR_SW_SHARE0_OUTPUT_1
+ 4'b 1111, // index[34] KEYMGR_SW_SHARE0_OUTPUT_2
+ 4'b 1111, // index[35] KEYMGR_SW_SHARE0_OUTPUT_3
+ 4'b 1111, // index[36] KEYMGR_SW_SHARE0_OUTPUT_4
+ 4'b 1111, // index[37] KEYMGR_SW_SHARE0_OUTPUT_5
+ 4'b 1111, // index[38] KEYMGR_SW_SHARE0_OUTPUT_6
+ 4'b 1111, // index[39] KEYMGR_SW_SHARE0_OUTPUT_7
+ 4'b 1111, // index[40] KEYMGR_SW_SHARE1_OUTPUT_0
+ 4'b 1111, // index[41] KEYMGR_SW_SHARE1_OUTPUT_1
+ 4'b 1111, // index[42] KEYMGR_SW_SHARE1_OUTPUT_2
+ 4'b 1111, // index[43] KEYMGR_SW_SHARE1_OUTPUT_3
+ 4'b 1111, // index[44] KEYMGR_SW_SHARE1_OUTPUT_4
+ 4'b 1111, // index[45] KEYMGR_SW_SHARE1_OUTPUT_5
+ 4'b 1111, // index[46] KEYMGR_SW_SHARE1_OUTPUT_6
+ 4'b 1111, // index[47] KEYMGR_SW_SHARE1_OUTPUT_7
+ 4'b 0001, // index[48] KEYMGR_WORKING_STATE
+ 4'b 0001, // index[49] KEYMGR_OP_STATUS
+ 4'b 0001 // index[50] KEYMGR_ERR_CODE
};
endpackage
diff --git a/hw/ip/keymgr/rtl/keymgr_reg_top.sv b/hw/ip/keymgr/rtl/keymgr_reg_top.sv
index 7cb6268..6d0e2e1 100644
--- a/hw/ip/keymgr/rtl/keymgr_reg_top.sv
+++ b/hw/ip/keymgr/rtl/keymgr_reg_top.sv
@@ -145,6 +145,18 @@
logic [31:0] sw_binding_3_qs;
logic [31:0] sw_binding_3_wd;
logic sw_binding_3_we;
+ logic [31:0] sw_binding_4_qs;
+ logic [31:0] sw_binding_4_wd;
+ logic sw_binding_4_we;
+ logic [31:0] sw_binding_5_qs;
+ logic [31:0] sw_binding_5_wd;
+ logic sw_binding_5_we;
+ logic [31:0] sw_binding_6_qs;
+ logic [31:0] sw_binding_6_wd;
+ logic sw_binding_6_we;
+ logic [31:0] sw_binding_7_qs;
+ logic [31:0] sw_binding_7_wd;
+ logic sw_binding_7_we;
logic [31:0] salt_0_qs;
logic [31:0] salt_0_wd;
logic salt_0_we;
@@ -157,6 +169,18 @@
logic [31:0] salt_3_qs;
logic [31:0] salt_3_wd;
logic salt_3_we;
+ logic [31:0] salt_4_qs;
+ logic [31:0] salt_4_wd;
+ logic salt_4_we;
+ logic [31:0] salt_5_qs;
+ logic [31:0] salt_5_wd;
+ logic salt_5_we;
+ logic [31:0] salt_6_qs;
+ logic [31:0] salt_6_wd;
+ logic salt_6_we;
+ logic [31:0] salt_7_qs;
+ logic [31:0] salt_7_wd;
+ logic salt_7_we;
logic [31:0] key_version_qs;
logic [31:0] key_version_wd;
logic key_version_we;
@@ -621,6 +645,114 @@
.qs (sw_binding_3_qs)
);
+ // Subregister 4 of Multireg sw_binding
+ // R[sw_binding_4]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_sw_binding_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (sw_binding_4_we & sw_binding_regwen_qs),
+ .wd (sw_binding_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_binding[4].q ),
+
+ // to register interface (read)
+ .qs (sw_binding_4_qs)
+ );
+
+ // Subregister 5 of Multireg sw_binding
+ // R[sw_binding_5]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_sw_binding_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (sw_binding_5_we & sw_binding_regwen_qs),
+ .wd (sw_binding_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_binding[5].q ),
+
+ // to register interface (read)
+ .qs (sw_binding_5_qs)
+ );
+
+ // Subregister 6 of Multireg sw_binding
+ // R[sw_binding_6]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_sw_binding_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (sw_binding_6_we & sw_binding_regwen_qs),
+ .wd (sw_binding_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_binding[6].q ),
+
+ // to register interface (read)
+ .qs (sw_binding_6_qs)
+ );
+
+ // Subregister 7 of Multireg sw_binding
+ // R[sw_binding_7]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_sw_binding_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (sw_binding_7_we & sw_binding_regwen_qs),
+ .wd (sw_binding_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_binding[7].q ),
+
+ // to register interface (read)
+ .qs (sw_binding_7_qs)
+ );
+
// Subregister 0 of Multireg salt
@@ -731,6 +863,114 @@
.qs (salt_3_qs)
);
+ // Subregister 4 of Multireg salt
+ // R[salt_4]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_salt_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (salt_4_we & cfg_regwen_qs),
+ .wd (salt_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.salt[4].q ),
+
+ // to register interface (read)
+ .qs (salt_4_qs)
+ );
+
+ // Subregister 5 of Multireg salt
+ // R[salt_5]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_salt_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (salt_5_we & cfg_regwen_qs),
+ .wd (salt_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.salt[5].q ),
+
+ // to register interface (read)
+ .qs (salt_5_qs)
+ );
+
+ // Subregister 6 of Multireg salt
+ // R[salt_6]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_salt_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (salt_6_we & cfg_regwen_qs),
+ .wd (salt_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.salt[6].q ),
+
+ // to register interface (read)
+ .qs (salt_6_qs)
+ );
+
+ // Subregister 7 of Multireg salt
+ // R[salt_7]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_salt_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (salt_7_we & cfg_regwen_qs),
+ .wd (salt_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.salt[7].q ),
+
+ // to register interface (read)
+ .qs (salt_7_qs)
+ );
+
// Subregister 0 of Multireg key_version
@@ -1520,7 +1760,7 @@
- logic [42:0] addr_hit;
+ logic [50:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == KEYMGR_INTR_STATE_OFFSET);
@@ -1536,36 +1776,44 @@
addr_hit[10] = (reg_addr == KEYMGR_SW_BINDING_1_OFFSET);
addr_hit[11] = (reg_addr == KEYMGR_SW_BINDING_2_OFFSET);
addr_hit[12] = (reg_addr == KEYMGR_SW_BINDING_3_OFFSET);
- addr_hit[13] = (reg_addr == KEYMGR_SALT_0_OFFSET);
- addr_hit[14] = (reg_addr == KEYMGR_SALT_1_OFFSET);
- addr_hit[15] = (reg_addr == KEYMGR_SALT_2_OFFSET);
- addr_hit[16] = (reg_addr == KEYMGR_SALT_3_OFFSET);
- addr_hit[17] = (reg_addr == KEYMGR_KEY_VERSION_OFFSET);
- addr_hit[18] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET);
- addr_hit[19] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_OFFSET);
- addr_hit[20] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET);
- addr_hit[21] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_OFFSET);
- addr_hit[22] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET);
- addr_hit[23] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_OFFSET);
- addr_hit[24] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET);
- addr_hit[25] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET);
- addr_hit[26] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET);
- addr_hit[27] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET);
- addr_hit[28] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET);
- addr_hit[29] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET);
- addr_hit[30] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET);
- addr_hit[31] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET);
- addr_hit[32] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET);
- addr_hit[33] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET);
- addr_hit[34] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET);
- addr_hit[35] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET);
- addr_hit[36] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET);
- addr_hit[37] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET);
- addr_hit[38] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET);
- addr_hit[39] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET);
- addr_hit[40] = (reg_addr == KEYMGR_WORKING_STATE_OFFSET);
- addr_hit[41] = (reg_addr == KEYMGR_OP_STATUS_OFFSET);
- addr_hit[42] = (reg_addr == KEYMGR_ERR_CODE_OFFSET);
+ addr_hit[13] = (reg_addr == KEYMGR_SW_BINDING_4_OFFSET);
+ addr_hit[14] = (reg_addr == KEYMGR_SW_BINDING_5_OFFSET);
+ addr_hit[15] = (reg_addr == KEYMGR_SW_BINDING_6_OFFSET);
+ addr_hit[16] = (reg_addr == KEYMGR_SW_BINDING_7_OFFSET);
+ addr_hit[17] = (reg_addr == KEYMGR_SALT_0_OFFSET);
+ addr_hit[18] = (reg_addr == KEYMGR_SALT_1_OFFSET);
+ addr_hit[19] = (reg_addr == KEYMGR_SALT_2_OFFSET);
+ addr_hit[20] = (reg_addr == KEYMGR_SALT_3_OFFSET);
+ addr_hit[21] = (reg_addr == KEYMGR_SALT_4_OFFSET);
+ addr_hit[22] = (reg_addr == KEYMGR_SALT_5_OFFSET);
+ addr_hit[23] = (reg_addr == KEYMGR_SALT_6_OFFSET);
+ addr_hit[24] = (reg_addr == KEYMGR_SALT_7_OFFSET);
+ addr_hit[25] = (reg_addr == KEYMGR_KEY_VERSION_OFFSET);
+ addr_hit[26] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_REGWEN_OFFSET);
+ addr_hit[27] = (reg_addr == KEYMGR_MAX_CREATOR_KEY_VER_OFFSET);
+ addr_hit[28] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_REGWEN_OFFSET);
+ addr_hit[29] = (reg_addr == KEYMGR_MAX_OWNER_INT_KEY_VER_OFFSET);
+ addr_hit[30] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_REGWEN_OFFSET);
+ addr_hit[31] = (reg_addr == KEYMGR_MAX_OWNER_KEY_VER_OFFSET);
+ addr_hit[32] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_0_OFFSET);
+ addr_hit[33] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_1_OFFSET);
+ addr_hit[34] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_2_OFFSET);
+ addr_hit[35] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_3_OFFSET);
+ addr_hit[36] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_4_OFFSET);
+ addr_hit[37] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_5_OFFSET);
+ addr_hit[38] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_6_OFFSET);
+ addr_hit[39] = (reg_addr == KEYMGR_SW_SHARE0_OUTPUT_7_OFFSET);
+ addr_hit[40] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_0_OFFSET);
+ addr_hit[41] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_1_OFFSET);
+ addr_hit[42] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_2_OFFSET);
+ addr_hit[43] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_3_OFFSET);
+ addr_hit[44] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_4_OFFSET);
+ addr_hit[45] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_5_OFFSET);
+ addr_hit[46] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_6_OFFSET);
+ addr_hit[47] = (reg_addr == KEYMGR_SW_SHARE1_OUTPUT_7_OFFSET);
+ addr_hit[48] = (reg_addr == KEYMGR_WORKING_STATE_OFFSET);
+ addr_hit[49] = (reg_addr == KEYMGR_OP_STATUS_OFFSET);
+ addr_hit[50] = (reg_addr == KEYMGR_ERR_CODE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -1616,6 +1864,14 @@
if (addr_hit[40] && reg_we && (KEYMGR_PERMIT[40] != (KEYMGR_PERMIT[40] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[41] && reg_we && (KEYMGR_PERMIT[41] != (KEYMGR_PERMIT[41] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[42] && reg_we && (KEYMGR_PERMIT[42] != (KEYMGR_PERMIT[42] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[43] && reg_we && (KEYMGR_PERMIT[43] != (KEYMGR_PERMIT[43] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[44] && reg_we && (KEYMGR_PERMIT[44] != (KEYMGR_PERMIT[44] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[45] && reg_we && (KEYMGR_PERMIT[45] != (KEYMGR_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[46] && reg_we && (KEYMGR_PERMIT[46] != (KEYMGR_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[47] && reg_we && (KEYMGR_PERMIT[47] != (KEYMGR_PERMIT[47] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[48] && reg_we && (KEYMGR_PERMIT[48] != (KEYMGR_PERMIT[48] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[49] && reg_we && (KEYMGR_PERMIT[49] != (KEYMGR_PERMIT[49] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[50] && reg_we && (KEYMGR_PERMIT[50] != (KEYMGR_PERMIT[50] & reg_be))) wr_err = 1'b1 ;
end
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
@@ -1666,100 +1922,124 @@
assign sw_binding_3_we = addr_hit[12] & reg_we & !reg_error;
assign sw_binding_3_wd = reg_wdata[31:0];
- assign salt_0_we = addr_hit[13] & reg_we & !reg_error;
+ assign sw_binding_4_we = addr_hit[13] & reg_we & !reg_error;
+ assign sw_binding_4_wd = reg_wdata[31:0];
+
+ assign sw_binding_5_we = addr_hit[14] & reg_we & !reg_error;
+ assign sw_binding_5_wd = reg_wdata[31:0];
+
+ assign sw_binding_6_we = addr_hit[15] & reg_we & !reg_error;
+ assign sw_binding_6_wd = reg_wdata[31:0];
+
+ assign sw_binding_7_we = addr_hit[16] & reg_we & !reg_error;
+ assign sw_binding_7_wd = reg_wdata[31:0];
+
+ assign salt_0_we = addr_hit[17] & reg_we & !reg_error;
assign salt_0_wd = reg_wdata[31:0];
- assign salt_1_we = addr_hit[14] & reg_we & !reg_error;
+ assign salt_1_we = addr_hit[18] & reg_we & !reg_error;
assign salt_1_wd = reg_wdata[31:0];
- assign salt_2_we = addr_hit[15] & reg_we & !reg_error;
+ assign salt_2_we = addr_hit[19] & reg_we & !reg_error;
assign salt_2_wd = reg_wdata[31:0];
- assign salt_3_we = addr_hit[16] & reg_we & !reg_error;
+ assign salt_3_we = addr_hit[20] & reg_we & !reg_error;
assign salt_3_wd = reg_wdata[31:0];
- assign key_version_we = addr_hit[17] & reg_we & !reg_error;
+ assign salt_4_we = addr_hit[21] & reg_we & !reg_error;
+ assign salt_4_wd = reg_wdata[31:0];
+
+ assign salt_5_we = addr_hit[22] & reg_we & !reg_error;
+ assign salt_5_wd = reg_wdata[31:0];
+
+ assign salt_6_we = addr_hit[23] & reg_we & !reg_error;
+ assign salt_6_wd = reg_wdata[31:0];
+
+ assign salt_7_we = addr_hit[24] & reg_we & !reg_error;
+ assign salt_7_wd = reg_wdata[31:0];
+
+ assign key_version_we = addr_hit[25] & reg_we & !reg_error;
assign key_version_wd = reg_wdata[31:0];
- assign max_creator_key_ver_regwen_we = addr_hit[18] & reg_we & !reg_error;
+ assign max_creator_key_ver_regwen_we = addr_hit[26] & reg_we & !reg_error;
assign max_creator_key_ver_regwen_wd = reg_wdata[0];
- assign max_creator_key_ver_we = addr_hit[19] & reg_we & !reg_error;
+ assign max_creator_key_ver_we = addr_hit[27] & reg_we & !reg_error;
assign max_creator_key_ver_wd = reg_wdata[31:0];
- assign max_owner_int_key_ver_regwen_we = addr_hit[20] & reg_we & !reg_error;
+ assign max_owner_int_key_ver_regwen_we = addr_hit[28] & reg_we & !reg_error;
assign max_owner_int_key_ver_regwen_wd = reg_wdata[0];
- assign max_owner_int_key_ver_we = addr_hit[21] & reg_we & !reg_error;
+ assign max_owner_int_key_ver_we = addr_hit[29] & reg_we & !reg_error;
assign max_owner_int_key_ver_wd = reg_wdata[31:0];
- assign max_owner_key_ver_regwen_we = addr_hit[22] & reg_we & !reg_error;
+ assign max_owner_key_ver_regwen_we = addr_hit[30] & reg_we & !reg_error;
assign max_owner_key_ver_regwen_wd = reg_wdata[0];
- assign max_owner_key_ver_we = addr_hit[23] & reg_we & !reg_error;
+ assign max_owner_key_ver_we = addr_hit[31] & reg_we & !reg_error;
assign max_owner_key_ver_wd = reg_wdata[31:0];
- assign sw_share0_output_0_we = addr_hit[24] & reg_re & !reg_error;
+ assign sw_share0_output_0_we = addr_hit[32] & reg_re & !reg_error;
assign sw_share0_output_0_wd = '1;
- assign sw_share0_output_1_we = addr_hit[25] & reg_re & !reg_error;
+ assign sw_share0_output_1_we = addr_hit[33] & reg_re & !reg_error;
assign sw_share0_output_1_wd = '1;
- assign sw_share0_output_2_we = addr_hit[26] & reg_re & !reg_error;
+ assign sw_share0_output_2_we = addr_hit[34] & reg_re & !reg_error;
assign sw_share0_output_2_wd = '1;
- assign sw_share0_output_3_we = addr_hit[27] & reg_re & !reg_error;
+ assign sw_share0_output_3_we = addr_hit[35] & reg_re & !reg_error;
assign sw_share0_output_3_wd = '1;
- assign sw_share0_output_4_we = addr_hit[28] & reg_re & !reg_error;
+ assign sw_share0_output_4_we = addr_hit[36] & reg_re & !reg_error;
assign sw_share0_output_4_wd = '1;
- assign sw_share0_output_5_we = addr_hit[29] & reg_re & !reg_error;
+ assign sw_share0_output_5_we = addr_hit[37] & reg_re & !reg_error;
assign sw_share0_output_5_wd = '1;
- assign sw_share0_output_6_we = addr_hit[30] & reg_re & !reg_error;
+ assign sw_share0_output_6_we = addr_hit[38] & reg_re & !reg_error;
assign sw_share0_output_6_wd = '1;
- assign sw_share0_output_7_we = addr_hit[31] & reg_re & !reg_error;
+ assign sw_share0_output_7_we = addr_hit[39] & reg_re & !reg_error;
assign sw_share0_output_7_wd = '1;
- assign sw_share1_output_0_we = addr_hit[32] & reg_re & !reg_error;
+ assign sw_share1_output_0_we = addr_hit[40] & reg_re & !reg_error;
assign sw_share1_output_0_wd = '1;
- assign sw_share1_output_1_we = addr_hit[33] & reg_re & !reg_error;
+ assign sw_share1_output_1_we = addr_hit[41] & reg_re & !reg_error;
assign sw_share1_output_1_wd = '1;
- assign sw_share1_output_2_we = addr_hit[34] & reg_re & !reg_error;
+ assign sw_share1_output_2_we = addr_hit[42] & reg_re & !reg_error;
assign sw_share1_output_2_wd = '1;
- assign sw_share1_output_3_we = addr_hit[35] & reg_re & !reg_error;
+ assign sw_share1_output_3_we = addr_hit[43] & reg_re & !reg_error;
assign sw_share1_output_3_wd = '1;
- assign sw_share1_output_4_we = addr_hit[36] & reg_re & !reg_error;
+ assign sw_share1_output_4_we = addr_hit[44] & reg_re & !reg_error;
assign sw_share1_output_4_wd = '1;
- assign sw_share1_output_5_we = addr_hit[37] & reg_re & !reg_error;
+ assign sw_share1_output_5_we = addr_hit[45] & reg_re & !reg_error;
assign sw_share1_output_5_wd = '1;
- assign sw_share1_output_6_we = addr_hit[38] & reg_re & !reg_error;
+ assign sw_share1_output_6_we = addr_hit[46] & reg_re & !reg_error;
assign sw_share1_output_6_wd = '1;
- assign sw_share1_output_7_we = addr_hit[39] & reg_re & !reg_error;
+ assign sw_share1_output_7_we = addr_hit[47] & reg_re & !reg_error;
assign sw_share1_output_7_wd = '1;
- assign op_status_we = addr_hit[41] & reg_we & !reg_error;
+ assign op_status_we = addr_hit[49] & reg_we & !reg_error;
assign op_status_wd = reg_wdata[1:0];
- assign err_code_invalid_op_we = addr_hit[42] & reg_we & !reg_error;
+ assign err_code_invalid_op_we = addr_hit[50] & reg_we & !reg_error;
assign err_code_invalid_op_wd = reg_wdata[0];
- assign err_code_invalid_cmd_we = addr_hit[42] & reg_we & !reg_error;
+ assign err_code_invalid_cmd_we = addr_hit[50] & reg_we & !reg_error;
assign err_code_invalid_cmd_wd = reg_wdata[1];
- assign err_code_invalid_kmac_input_we = addr_hit[42] & reg_we & !reg_error;
+ assign err_code_invalid_kmac_input_we = addr_hit[50] & reg_we & !reg_error;
assign err_code_invalid_kmac_input_wd = reg_wdata[2];
- assign err_code_invalid_kmac_data_we = addr_hit[42] & reg_we & !reg_error;
+ assign err_code_invalid_kmac_data_we = addr_hit[50] & reg_we & !reg_error;
assign err_code_invalid_kmac_data_wd = reg_wdata[3];
// Read data return
@@ -1822,122 +2102,154 @@
end
addr_hit[13]: begin
- reg_rdata_next[31:0] = salt_0_qs;
+ reg_rdata_next[31:0] = sw_binding_4_qs;
end
addr_hit[14]: begin
- reg_rdata_next[31:0] = salt_1_qs;
+ reg_rdata_next[31:0] = sw_binding_5_qs;
end
addr_hit[15]: begin
- reg_rdata_next[31:0] = salt_2_qs;
+ reg_rdata_next[31:0] = sw_binding_6_qs;
end
addr_hit[16]: begin
- reg_rdata_next[31:0] = salt_3_qs;
+ reg_rdata_next[31:0] = sw_binding_7_qs;
end
addr_hit[17]: begin
- reg_rdata_next[31:0] = key_version_qs;
+ reg_rdata_next[31:0] = salt_0_qs;
end
addr_hit[18]: begin
- reg_rdata_next[0] = max_creator_key_ver_regwen_qs;
+ reg_rdata_next[31:0] = salt_1_qs;
end
addr_hit[19]: begin
- reg_rdata_next[31:0] = max_creator_key_ver_qs;
+ reg_rdata_next[31:0] = salt_2_qs;
end
addr_hit[20]: begin
- reg_rdata_next[0] = max_owner_int_key_ver_regwen_qs;
+ reg_rdata_next[31:0] = salt_3_qs;
end
addr_hit[21]: begin
- reg_rdata_next[31:0] = max_owner_int_key_ver_qs;
+ reg_rdata_next[31:0] = salt_4_qs;
end
addr_hit[22]: begin
- reg_rdata_next[0] = max_owner_key_ver_regwen_qs;
+ reg_rdata_next[31:0] = salt_5_qs;
end
addr_hit[23]: begin
- reg_rdata_next[31:0] = max_owner_key_ver_qs;
+ reg_rdata_next[31:0] = salt_6_qs;
end
addr_hit[24]: begin
- reg_rdata_next[31:0] = sw_share0_output_0_qs;
+ reg_rdata_next[31:0] = salt_7_qs;
end
addr_hit[25]: begin
- reg_rdata_next[31:0] = sw_share0_output_1_qs;
+ reg_rdata_next[31:0] = key_version_qs;
end
addr_hit[26]: begin
- reg_rdata_next[31:0] = sw_share0_output_2_qs;
+ reg_rdata_next[0] = max_creator_key_ver_regwen_qs;
end
addr_hit[27]: begin
- reg_rdata_next[31:0] = sw_share0_output_3_qs;
+ reg_rdata_next[31:0] = max_creator_key_ver_qs;
end
addr_hit[28]: begin
- reg_rdata_next[31:0] = sw_share0_output_4_qs;
+ reg_rdata_next[0] = max_owner_int_key_ver_regwen_qs;
end
addr_hit[29]: begin
- reg_rdata_next[31:0] = sw_share0_output_5_qs;
+ reg_rdata_next[31:0] = max_owner_int_key_ver_qs;
end
addr_hit[30]: begin
- reg_rdata_next[31:0] = sw_share0_output_6_qs;
+ reg_rdata_next[0] = max_owner_key_ver_regwen_qs;
end
addr_hit[31]: begin
- reg_rdata_next[31:0] = sw_share0_output_7_qs;
+ reg_rdata_next[31:0] = max_owner_key_ver_qs;
end
addr_hit[32]: begin
- reg_rdata_next[31:0] = sw_share1_output_0_qs;
+ reg_rdata_next[31:0] = sw_share0_output_0_qs;
end
addr_hit[33]: begin
- reg_rdata_next[31:0] = sw_share1_output_1_qs;
+ reg_rdata_next[31:0] = sw_share0_output_1_qs;
end
addr_hit[34]: begin
- reg_rdata_next[31:0] = sw_share1_output_2_qs;
+ reg_rdata_next[31:0] = sw_share0_output_2_qs;
end
addr_hit[35]: begin
- reg_rdata_next[31:0] = sw_share1_output_3_qs;
+ reg_rdata_next[31:0] = sw_share0_output_3_qs;
end
addr_hit[36]: begin
- reg_rdata_next[31:0] = sw_share1_output_4_qs;
+ reg_rdata_next[31:0] = sw_share0_output_4_qs;
end
addr_hit[37]: begin
- reg_rdata_next[31:0] = sw_share1_output_5_qs;
+ reg_rdata_next[31:0] = sw_share0_output_5_qs;
end
addr_hit[38]: begin
- reg_rdata_next[31:0] = sw_share1_output_6_qs;
+ reg_rdata_next[31:0] = sw_share0_output_6_qs;
end
addr_hit[39]: begin
- reg_rdata_next[31:0] = sw_share1_output_7_qs;
+ reg_rdata_next[31:0] = sw_share0_output_7_qs;
end
addr_hit[40]: begin
- reg_rdata_next[2:0] = working_state_qs;
+ reg_rdata_next[31:0] = sw_share1_output_0_qs;
end
addr_hit[41]: begin
- reg_rdata_next[1:0] = op_status_qs;
+ reg_rdata_next[31:0] = sw_share1_output_1_qs;
end
addr_hit[42]: begin
+ reg_rdata_next[31:0] = sw_share1_output_2_qs;
+ end
+
+ addr_hit[43]: begin
+ reg_rdata_next[31:0] = sw_share1_output_3_qs;
+ end
+
+ addr_hit[44]: begin
+ reg_rdata_next[31:0] = sw_share1_output_4_qs;
+ end
+
+ addr_hit[45]: begin
+ reg_rdata_next[31:0] = sw_share1_output_5_qs;
+ end
+
+ addr_hit[46]: begin
+ reg_rdata_next[31:0] = sw_share1_output_6_qs;
+ end
+
+ addr_hit[47]: begin
+ reg_rdata_next[31:0] = sw_share1_output_7_qs;
+ end
+
+ addr_hit[48]: begin
+ reg_rdata_next[2:0] = working_state_qs;
+ end
+
+ addr_hit[49]: begin
+ reg_rdata_next[1:0] = op_status_qs;
+ end
+
+ addr_hit[50]: begin
reg_rdata_next[0] = err_code_invalid_op_qs;
reg_rdata_next[1] = err_code_invalid_cmd_qs;
reg_rdata_next[2] = err_code_invalid_kmac_input_qs;
