tree: 848b45db361ac1396695b193966107c23f55e599 [path history] [tgz]
  1. cov/
  2. env/
  3. tb/
  4. tests/
  5. chip_sim.core
  6. chip_sim_cfg.hjson
  7. Makefile
  8. README.md
  9. top_earlgrey_sim_cfgs.hjson
hw/top_earlgrey/dv/README.md

TOP Earl Grey

How to run simulation

Please run the following command to build and run tests: make TEST_NAME=<test-name>

Please see adjoining Makefile file for list of available tests to run. Please see hw/dv/tools/README.md for additional details on options that can be passed (such as enabling waves, running with specific seed etc.).

Note: Currently, ibex core raises an assertion but it doesn't harm UART TX and GPIO functionalities. Please ignore until it is resolved.