[flash_ctrl] Connect flash / pwrmgr functions
- Connect init / done
- Connect idle
Signed-off-by: Timothy Chen <timothytim@google.com>
[flash_ctrl] update waivers
Signed-off-by: Timothy Chen <timothytim@google.com>
[flash_ctrl] fix typos
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index f420430..c214965 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -36,13 +36,20 @@
package: "flash_ctrl_pkg"
},
- { struct: "pwrmgr_flash",
+ { struct: "edn_entropy",
type: "uni",
- name: "pwrmgr",
+ name: "edn",
act: "rcv",
package: "flash_ctrl_pkg"
},
+ { struct: "pwr_flash",
+ type: "req_rsp",
+ name: "pwrmgr",
+ act: "rsp",
+ package: "pwrmgr_pkg"
+ },
+
],
param_list: [
diff --git a/hw/ip/flash_ctrl/dv/tb/flash_ctrl_wrapper.sv b/hw/ip/flash_ctrl/dv/tb/flash_ctrl_wrapper.sv
index e4facd1..b903f01 100644
--- a/hw/ip/flash_ctrl/dv/tb/flash_ctrl_wrapper.sv
+++ b/hw/ip/flash_ctrl/dv/tb/flash_ctrl_wrapper.sv
@@ -17,7 +17,8 @@
// OTP interface
input flash_ctrl_pkg::otp_flash_t otp_i,
input flash_ctrl_pkg::lc_flash_req_t lc_i,
- input flash_ctrl_pkg::pwrmgr_flash_t pwrmgr_i,
+ output pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
+ input pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
input flash_ctrl_pkg::edn_entropy_t edn_i,
// Interrupts
@@ -51,6 +52,7 @@
.otp_i (otp_i),
.lc_i (lc_i),
.pwrmgr_i (pwrmgr_i),
+ .pwrmgr_o (pwrmgr_o),
.edn_i (edn_i),
.clk_i (clk_i),
diff --git a/hw/ip/flash_ctrl/dv/tb/tb.sv b/hw/ip/flash_ctrl/dv/tb/tb.sv
index fa564df..c6b08a1 100644
--- a/hw/ip/flash_ctrl/dv/tb/tb.sv
+++ b/hw/ip/flash_ctrl/dv/tb/tb.sv
@@ -46,7 +46,8 @@
// TODO: create and hook this up to an interface.
.otp_i (flash_ctrl_pkg::OTP_FLASH_DEFAULT),
.lc_i (flash_ctrl_pkg::LC_FLASH_REQ_DEFAULT),
- .pwrmgr_i (flash_ctrl_pkg::PWRMGR_FLASH_DEFAULT),
+ .pwrmgr_o (pwrmgr_pkg::PWR_FLASH_RSP_DEFAULT),
+ .pwrmgr_i (pwrmgr_pkg::PWR_FLASH_REQ_DEFAULT),
.edn_i (flash_ctrl_pkg::EDN_ENTROPY_DEFAULT),
.intr_prog_empty_o (intr_prog_empty),
diff --git a/hw/ip/flash_ctrl/flash_ctrl.core b/hw/ip/flash_ctrl/flash_ctrl.core
index 2280904..b760c47 100644
--- a/hw/ip/flash_ctrl/flash_ctrl.core
+++ b/hw/ip/flash_ctrl/flash_ctrl.core
@@ -14,6 +14,7 @@
- lowrisc:prim:lfsr
- lowrisc:prim:flash
- lowrisc:prim:gf_mult
+ - lowrisc:ip:pwrmgr_pkg
- lowrisc:ip:flash_ctrl_pkg
files:
- rtl/flash_ctrl_reg_top.sv
diff --git a/hw/ip/flash_ctrl/lint/flash_ctrl.waiver b/hw/ip/flash_ctrl/lint/flash_ctrl.waiver
index 25a4d5d..192c86b 100644
--- a/hw/ip/flash_ctrl/lint/flash_ctrl.waiver
+++ b/hw/ip/flash_ctrl/lint/flash_ctrl.waiver
@@ -7,3 +7,14 @@
# All leaf resets have a reset multiplex
waive -rules TERMINAL_STATE -location {flash_ctrl_lcmgr.sv} -regexp {.*StInvalid.*} \
-comment "StInvalid is intended to be a terminal state"
+
+# Remove errors from prim_* modules
+# TBD These should be directly addressed in primgen modules long term
+waive -rules INPUT_NOT_READ -location {prim_flop.sv} -regexp {Input port.*} \
+ -comment "Silience prim related errors"
+
+waive -rules OUTPUT_NOT_DRIVEN -location {prim_flop*.sv} -regexp {.*q_o.*} \
+ -comment "Silience prim related errors"
+
+waive -rules INPUT_NOT_READ -location {prim_flop_2sync.sv} -regexp {Input port.*} \
+ -comment "Silience prim related errors"
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index aacc643..71c69b1 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -24,7 +24,8 @@
input otp_flash_t otp_i,
input lc_flash_req_t lc_i,
output lc_flash_rsp_t lc_o,
- input pwrmgr_flash_t pwrmgr_i,
+ input pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
+ output pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
input edn_entropy_t edn_i,
// Interrupts
@@ -269,7 +270,8 @@
.clk_i,
.rst_ni,
- .init_i(pwrmgr_i.init),
+ .init_i(pwrmgr_i.flash_init),
+ .init_done_o(pwrmgr_o.flash_done),
.provision_en_i(lc_i.provision_en),
// interface to ctrl arb control ports
@@ -385,9 +387,6 @@
.flash_error_i (flash_mp_error)
);
- // Read FIFO
-
-
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
adapter_rvalid <= 1'b0;
@@ -636,6 +635,23 @@
assign flash_rd_data = flash_i.rd_data;
assign flash_phy_busy = flash_i.init_busy;
+ // Interface to pwrmgr
+ // flash is not idle as long as there is a stateful operation ongoing
+ logic flash_idle_d;
+ assign flash_idle_d = ~(flash_o.req &
+ (flash_o.prog | flash_o.pg_erase | flash_o.bk_erase));
+
+ prim_flop #(
+ .Width(1),
+ .ResetValue(1'b1)
+ ) u_reg_idle (
+ .clk_i,
+ .rst_ni,
+ .d_i(flash_idle_d),
+ .q_o(pwrmgr_o.flash_idle)
+ );
+
+
// Interrupts
// Generate edge triggered signals for sources that are level
logic [3:0] intr_src;
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_arb.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_arb.sv
index 181588d..f14534c 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_arb.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_arb.sv
@@ -60,7 +60,7 @@
output logic prog_fifo_wvalid_o,
input logic prog_fifo_wready_i,
- // flash phy initilization ongoing
+ // flash phy initialization ongoing
input logic flash_phy_busy_i,
// clear fifo contents
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
index fcf14f0..cd32191 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
@@ -11,6 +11,7 @@
// initialization command
input init_i,
+ output logic init_done_o,
// only access seeds when provisioned
input provision_en_i,
@@ -81,6 +82,7 @@
} state_e;
state_e state_q, state_d;
+ logic init_done_d;
logic validate_q, validate_d;
logic [SeedCntWidth-1:0] seed_cnt_q;
logic [CntWidth-1:0] addr_cnt_q;
@@ -97,9 +99,11 @@
if (!rst_ni) begin
state_q <= StIdle;
validate_q <= 1'b0;
+ init_done_o <= 1'b0;
end else begin
state_q <= state_d;
validate_q <= validate_d;
+ init_done_o <= init_done_d;
end
end
@@ -175,6 +179,19 @@
// rma phase is erase unless we are validating
assign op = seed_phase || validate_q ? FlashOpRead : FlashOpErase;
+ // synchronize inputs
+ logic init_q;
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue(0)
+ ) u_sync_flash_init (
+ .clk_i,
+ .rst_ni,
+ .d_i(init_i),
+ .q_o(init_q)
+ );
+
always_comb begin
// phases of the hardware interface
@@ -202,15 +219,20 @@
state_d = state_q;
validate_d = validate_q;
+ // init status
+ // flash_ctrl handles its own arbitration between hardware and software.
+ // So once the init kicks off it is safe to ack. The done signal is still
+ // to give a chance to hold off further power up progression in the future
+ // if required.
+ init_done_d = 1'b1;
+
unique case (state_q)
StIdle: begin
+ init_done_d = 1'b0;
phase = PhaseSeed;
- // TBD: provision_en is only a "good" value after otp initilization
- // Need to qualify this statement with some notion that otp init has
- // finished. Since power manager will kick off otp init, it should
- // also be able to kick off flash_init
- if (init_i) begin
+ // provision_en is only a "good" value after otp/lc initialization
+ if (init_q) begin
// if provisioning is not enabled, do not read seeds and skip directly
// to wait state.
state_d = provision_en_i ? StReadSeeds : StWait;
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
index e7f23e1..336f9b6 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
@@ -282,11 +282,6 @@
logic [BusWidth-1:0] rma_ack_token;
} lc_flash_rsp_t;
- // pwrmgr to flash_ctrl
- typedef struct packed {
- logic init;
- } pwrmgr_flash_t;
-
// place holder for interface to EDN, replace with real one later
typedef struct packed {
logic valid;
@@ -309,10 +304,6 @@
provision_en: 1'b1
};
- parameter pwrmgr_flash_t PWRMGR_FLASH_DEFAULT = '{
- init: 1'b1
- };
-
parameter edn_entropy_t EDN_ENTROPY_DEFAULT = '{
valid: 1'b1,
entropy: '0
