[util, reggen] Support standardized cdc handling for regfile
- Support two asynchronous schemes on regfile
- Fully asynchronous - a tlul_fifo_async directly instantiated in regfile
- Mixed asynchronous - allow user to selectively mark registers as async
- These two schemes are mutually exclusive
- Add an 'async' key for bus interfaces to indicate the reg block is fully asynchornous
- Add an 'async' key per register to indicate register clock domain
- Add extra clock/reset ports to reg module
- Add prim_subreg_cdc to handle regiser domain clock crossing
Signed-off-by: Timothy Chen <timothytim@google.com>
[aon_timer] Updates to aon_timer to experiment with new cdc scheme
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/util/reggen/ip_block.py b/util/reggen/ip_block.py
index 06d473c..9a59d3c 100644
--- a/util/reggen/ip_block.py
+++ b/util/reggen/ip_block.py
@@ -202,8 +202,6 @@
scan = check_bool(rd.get('scan', False), 'scan field of ' + what)
- reg_blocks = RegBlock.build_blocks(init_block, rd['registers'])
-
r_inter_signals = check_list(rd.get('inter_signal_list', []),
'inter_signal_list field')
inter_signals = [
@@ -224,6 +222,10 @@
clocking = Clocking.from_raw(rd['clocking'],
'clocking field of ' + what)
+ reg_blocks = RegBlock.build_blocks(init_block, rd['registers'],
+ bus_interfaces,
+ clocking)
+
xputs = (
Signal.from_raw_list('available_inout_list for block ' + name,
rd.get('available_inout_list', [])),
