| commit | a3977744f32a20bbd43a162fac0ad323230b4d8f | [log] [tgz] |
|---|---|---|
| author | Weicai Yang <weicai@google.com> | Thu Oct 15 13:59:40 2020 -0700 |
| committer | sriyerg <46467186+sriyerg@users.noreply.github.com> | Fri Oct 16 12:01:00 2020 -0700 |
| tree | da407727fe92111028d5d048759cc71a61cd3b9e | |
| parent | 9c06e11624d478929d631a768277bbb5351cbb82 [diff] |
[dv/xbar] Fix xcelium warning chip xbar re-defines some macro as chip TB uses different way connect tl ports. I feel it's better to use another macro name rather than re-define existing macro. This will fix xcelium warning Signed-off-by: Weicai Yang <weicai@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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