commit a39557eb0b8f1bc90461b4bc90f7a22b49a410ec
author Michael Schaffner <msf@opentitan.org> Tue Mar 17 18:30:21 2020 -0700
committer Michael Schaffner <msf@google.com> Wed Mar 18 21:31:57 2020 -0700
tree 055cb2820e7f79fc8852820e798408825931b63a
parent 90eac34d56d7bcd0296d9156b4a3f2c2e4a6eb22

[top/usbdev] Compile error fix in usbdev and naming changes in toplevel

Signed-off-by: Michael Schaffner <msf@opentitan.org>

hw/top_earlgrey/data/top_earlgrey.sv.tpl

diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 834dfd9..fa7e585 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -246,7 +246,7 @@
     .DmHaltAddr          (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress),
     .DmExceptionAddr     (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress),
     .PipeLine            (IbexPipeLine)
-  ) core (
+  ) u_rv_core_ibex (
     // clock and reset
     .clk_i                (main_clk),
     .rst_ni               (sys_rst_n),
@@ -331,7 +331,7 @@
     .SramAw(${addr_width}),
     .SramDw(${data_width}),
     .Outstanding(2)
-  ) tl_adapter_${m["name"]} (
+  ) u_tl_adapter_${m["name"]} (
     % for key in clocks:
     .${key}   (${clocks[key]}_clk),
     % endfor
@@ -392,7 +392,7 @@
     .SramDw(${data_width}),
     .Outstanding(2),
     .ErrOnWrite(1)
-  ) tl_adapter_${m["name"]} (
+  ) u_tl_adapter_${m["name"]} (
     % for key in clocks:
     .${key}   (${clocks[key]}_clk),
     % endfor
@@ -456,7 +456,7 @@
     .Outstanding(2),
     .ByteAccess(0),
     .ErrOnWrite(1)
-  ) tl_adapter_${m["name"]} (
+  ) u_tl_adapter_${m["name"]} (
     % for key in clocks:
     .${key}   (${clocks[key]}_clk),
     % endfor
@@ -530,9 +530,9 @@
     .${k}(${v | lib.parameterize}),
         % endif
     % endfor
-  ) ${m["name"]} (
+  ) u_${m["name"]} (
   % else:
-  ${m["type"]} ${m["name"]} (
+  ${m["type"]} u_${m["name"]} (
   % endif
     % if not "bus_host" in m or m["bus_host"] in ["none", ""]:
       .tl_i (tl_${m["name"]}_d_h2d),