| commit | a384e3dd8adc901b4fc0353a2ffd31b036540bd0 | [log] [tgz] |
|---|---|---|
| author | Silvestrs Timofejevs <silvestrst@lowrisc.org> | Thu Oct 15 13:13:20 2020 +0100 |
| committer | Sam Elliott <sam@lenary.co.uk> | Wed Oct 21 17:49:57 2020 +0100 |
| tree | fb06d05b2c4739c0e853fe37c8dda1b9a028c0dc | |
| parent | bd749af6a99bea3cd0a624a23745d431d79d0ee7 [diff] |
[sw, MaskROM] Minor `mask_rom_start.S` improvements. - `mstatus` `mie` bit is cleared on reset. Volume II: RISC-V Privileged Architectures V20190608-Priv-MSU-Ratified: "3.3 Reset Upon reset, a hart’s privilege mode is set to M. The mstatus fields MIE and MPRV are reset to 0." - Reference to `boot.md` has been added in a comment. Signed-off-by: Silvestrs Timofejevs <silvestrst@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).