[otp_ctrl/top] Regenerate files
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index ce49627..27d01dd 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -2596,6 +2596,250 @@
]
}
{
+ name: otp_ctrl
+ type: otp_ctrl
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ clock_group: timers
+ reset_connections:
+ {
+ rst_ni: sys_io_div4
+ }
+ base_addr: 0x401b0000
+ clock_reset_export: []
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_io_div4_timers
+ }
+ size: 0x2000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list:
+ [
+ {
+ name: otp_operation_done
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: otp_error
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list:
+ [
+ {
+ name: otp_fatal_error
+ width: 1
+ type: alert
+ async: 1
+ }
+ {
+ name: otp_check_failed
+ width: 1
+ type: alert
+ async: 1
+ }
+ ]
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: otp_ast_req
+ type: uni
+ name: otp_ast_pwr_seq
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ external: true
+ top_signame: otp_ctrl_otp_ast_pwr_seq
+ index: -1
+ }
+ {
+ struct: otp_ast_rsp
+ type: uni
+ name: otp_ast_pwr_seq_h
+ act: rcv
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ external: true
+ top_signame: otp_ctrl_otp_ast_pwr_seq_h
+ index: -1
+ }
+ {
+ struct: otp_edn
+ type: req_rsp
+ name: otp_edn
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: pwr_otp
+ type: req_rsp
+ name: pwr_otp
+ act: rsp
+ default: "'0"
+ package: pwrmgr_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_otp_program
+ type: req_rsp
+ name: lc_otp_program
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_otp_token
+ type: req_rsp
+ name: lc_otp_token
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otp_lc_data
+ type: uni
+ name: otp_lc_data
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_escalate_en
+ act: rcv
+ default: "'0"
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_provision_en
+ act: rcv
+ default: "'0"
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_dft_en
+ act: rcv
+ default: "'0"
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otp_keymgr_key
+ type: uni
+ name: otp_keymgr_key
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: flash_otp_key
+ type: req_rsp
+ name: flash_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: sram_otp_key
+ width: "2"
+ type: req_rsp
+ name: sram_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otbn_otp_key
+ type: req_rsp
+ name: otbn_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: hw_cfg
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: otp_ctrl
+ width: 1
+ default: ""
+ top_signame: otp_ctrl_tl
+ index: -1
+ }
+ ]
+ }
+ {
name: otbn
type: otbn
clock_srcs:
@@ -3002,6 +3246,10 @@
[
peri.tl_ram_ret
]
+ otp_ctrl.tl:
+ [
+ peri.tl_otp_ctrl
+ ]
sensor_ctrl.tl:
[
peri.tl_sensor_ctrl
@@ -3031,6 +3279,8 @@
usbdev.usb_ref_val: ""
usbdev.usb_ref_pulse: ""
peri.tl_ast_wrapper: ast_tl
+ otp_ctrl.otp_ast_pwr_seq: ""
+ otp_ctrl.otp_ast_pwr_seq_h: ""
clkmgr.clocks_ast: clks_ast
rstmgr.resets_ast: rsts_ast
}
@@ -3243,6 +3493,10 @@
base_addr: 0x40170000
size_byte: 0x11000
}
+ {
+ base_addr: 0x401b0000
+ size_byte: 0x2000
+ }
]
}
{
@@ -3676,6 +3930,7 @@
rstmgr
clkmgr
ram_ret
+ otp_ctrl
sensor_ctrl
ast_wrapper
]
@@ -3856,6 +4111,24 @@
pipeline_byp: "true"
}
{
+ name: otp_ctrl
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: otp_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x401b0000
+ size_byte: 0x2000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
name: sensor_ctrl
type: device
clock: clk_peri_i
@@ -4018,6 +4291,18 @@
{
struct: tl
type: req_rsp
+ name: tl_otp_ctrl
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: otp_ctrl_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
name: tl_sensor_ctrl
act: req
package: tlul_pkg
@@ -4743,6 +5028,7 @@
otbn
sensor_ctrl
keymgr
+ otp_ctrl
]
alert:
[
@@ -4802,6 +5088,20 @@
async: 0
module_name: keymgr
}
+ {
+ name: otp_ctrl_otp_fatal_error
+ width: 1
+ type: alert
+ async: 1
+ module_name: otp_ctrl
+ }
+ {
+ name: otp_ctrl_otp_check_failed
+ width: 1
+ type: alert
+ async: 1
+ module_name: otp_ctrl
+ }
]
pinmux:
{
@@ -5944,6 +6244,175 @@
index: -1
}
{
+ struct: otp_ast_req
+ type: uni
+ name: otp_ast_pwr_seq
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ external: true
+ top_signame: otp_ctrl_otp_ast_pwr_seq
+ index: -1
+ }
+ {
+ struct: otp_ast_rsp
+ type: uni
+ name: otp_ast_pwr_seq_h
+ act: rcv
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ external: true
+ top_signame: otp_ctrl_otp_ast_pwr_seq_h
+ index: -1
+ }
+ {
+ struct: otp_edn
+ type: req_rsp
+ name: otp_edn
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: pwr_otp
+ type: req_rsp
+ name: pwr_otp
+ act: rsp
+ default: "'0"
+ package: pwrmgr_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_otp_program
+ type: req_rsp
+ name: lc_otp_program
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_otp_token
+ type: req_rsp
+ name: lc_otp_token
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otp_lc_data
+ type: uni
+ name: otp_lc_data
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_escalate_en
+ act: rcv
+ default: "'0"
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_provision_en
+ act: rcv
+ default: "'0"
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_dft_en
+ act: rcv
+ default: "'0"
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otp_keymgr_key
+ type: uni
+ name: otp_keymgr_key
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: flash_otp_key
+ type: req_rsp
+ name: flash_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: sram_otp_key
+ width: "2"
+ type: req_rsp
+ name: sram_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otbn_otp_key
+ type: req_rsp
+ name: otbn_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: hw_cfg
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: otp_ctrl
+ width: 1
+ default: ""
+ top_signame: otp_ctrl_tl
+ index: -1
+ }
+ {
name: idle
type: uni
struct: logic
@@ -6366,6 +6835,18 @@
{
struct: tl
type: req_rsp
+ name: tl_otp_ctrl
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: otp_ctrl_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
name: tl_sensor_ctrl
act: req
package: tlul_pkg
@@ -6518,6 +6999,24 @@
direction: in
}
{
+ package: otp_ctrl_pkg
+ struct: otp_ast_req
+ signame: otp_ctrl_otp_ast_pwr_seq_o
+ width: 1
+ type: uni
+ default: "'0"
+ direction: out
+ }
+ {
+ package: otp_ctrl_pkg
+ struct: otp_ast_rsp
+ signame: otp_ctrl_otp_ast_pwr_seq_h_i
+ width: 1
+ type: uni
+ default: "'0"
+ direction: in
+ }
+ {
package: clkmgr_pkg
struct: clkmgr_ast_out
signame: clks_ast_o
@@ -7013,6 +7512,22 @@
{
package: tlul_pkg
struct: tl_h2d
+ signame: otp_ctrl_tl_req
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_d2h
+ signame: otp_ctrl_tl_rsp
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_h2d
signame: sensor_ctrl_tl_req
width: 1
type: req_rsp
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 8a27256..4475b01 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -12,3 +12,5 @@
assign alert_if[5].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[2];
assign alert_if[6].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[0];
assign alert_if[7].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[8].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
+assign alert_if[9].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
index 0127aef..26c6cf4 100644
--- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -54,6 +54,7 @@
tl_if rstmgr_tl_if(clk_io_div4, rst_n);
tl_if clkmgr_tl_if(clk_io_div4, rst_n);
tl_if ram_ret_tl_if(clk_io_div4, rst_n);
+tl_if otp_ctrl_tl_if(clk_io_div4, rst_n);
tl_if sensor_ctrl_tl_if(clk_io_div4, rst_n);
tl_if ast_wrapper_tl_if(clk_io_div4, rst_n);
@@ -109,6 +110,7 @@
`DRIVE_TL_DEVICE_IF(rstmgr, rstmgr, tl)
`DRIVE_TL_DEVICE_IF(clkmgr, clkmgr, tl)
`DRIVE_TL_DEVICE_IF(ram_ret, tl_adapter_ram_ret, tl)
+ `DRIVE_TL_DEVICE_IF(otp_ctrl, otp_ctrl, tl)
`DRIVE_TL_DEVICE_IF(sensor_ctrl, sensor_ctrl, tl)
`DRIVE_TL_EXT_DEVICE_IF(ast_wrapper, ast_tl)
end
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
index bdb366e..6707db7 100644
--- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -76,6 +76,9 @@
'{"ram_ret", '{
'{32'h18000000, 32'h18000fff}
}},
+ '{"otp_ctrl", '{
+ '{32'h401b0000, 32'h401b1fff}
+ }},
'{"sensor_ctrl", '{
'{32'h40170000, 32'h40170fff}
}},
@@ -105,6 +108,7 @@
"rstmgr",
"clkmgr",
"ram_ret",
+ "otp_ctrl",
"sensor_ctrl",
"ast_wrapper",
"flash_ctrl",
@@ -131,6 +135,7 @@
"rstmgr",
"clkmgr",
"ram_ret",
+ "otp_ctrl",
"sensor_ctrl",
"ast_wrapper",
"flash_ctrl",
diff --git a/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv
index 7a9ab73..4e3af62 100644
--- a/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv
@@ -12,7 +12,9 @@
"otbn_dmem_uncorrectable",
"otbn_reg_uncorrectable",
"sensor_ctrl_ast_alerts",
- "keymgr_err"
+ "keymgr_err",
+ "otp_ctrl_otp_fatal_error",
+ "otp_ctrl_otp_check_failed"
};
-parameter uint NUM_ALERTS = 8;
+parameter uint NUM_ALERTS = 10;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index 18ac65e..1a34051 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -29,7 +29,7 @@
{ name: "NAlerts",
desc: "Number of peripheral inputs",
type: "int",
- default: "14",
+ default: "16",
local: "true"
},
{ name: "EscCntDw",
@@ -47,7 +47,7 @@
{ name: "AsyncOn",
desc: "Number of peripheral outputs",
type: "logic [NAlerts-1:0]",
- default: "14'b01111111000000",
+ default: "16'b1101111111000000",
local: "true"
},
{ name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
index 6aab9b6..456a74f 100644
--- a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
@@ -10,5 +10,5 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-parameter uint NUM_ALERTS = 14;
-parameter bit [NUM_ALERTS-1:0] ASYNC_ON = 14'b01111111000000;
+parameter uint NUM_ALERTS = 16;
+parameter bit [NUM_ALERTS-1:0] ASYNC_ON = 16'b1101111111000000;
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index 45bf3f4..d7bc901 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,10 +7,10 @@
package alert_handler_reg_pkg;
// Param list
- parameter int NAlerts = 14;
+ parameter int NAlerts = 16;
parameter int EscCntDw = 32;
parameter int AccuCntDw = 16;
- parameter logic [NAlerts-1:0] AsyncOn = 14'b01111111000000;
+ parameter logic [NAlerts-1:0] AsyncOn = 16'b1101111111000000;
parameter int N_CLASSES = 4;
parameter int N_ESC_SEV = 4;
parameter int N_PHASES = 4;
@@ -454,14 +454,14 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- alert_handler_reg2hw_intr_state_reg_t intr_state; // [880:877]
- alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [876:873]
- alert_handler_reg2hw_intr_test_reg_t intr_test; // [872:865]
- alert_handler_reg2hw_regen_reg_t regen; // [864:864]
- alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [863:840]
- alert_handler_reg2hw_alert_en_mreg_t [13:0] alert_en; // [839:826]
- alert_handler_reg2hw_alert_class_mreg_t [13:0] alert_class; // [825:798]
- alert_handler_reg2hw_alert_cause_mreg_t [13:0] alert_cause; // [797:784]
+ alert_handler_reg2hw_intr_state_reg_t intr_state; // [888:885]
+ alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [884:881]
+ alert_handler_reg2hw_intr_test_reg_t intr_test; // [880:873]
+ alert_handler_reg2hw_regen_reg_t regen; // [872:872]
+ alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [871:848]
+ alert_handler_reg2hw_alert_en_mreg_t [15:0] alert_en; // [847:832]
+ alert_handler_reg2hw_alert_class_mreg_t [15:0] alert_class; // [831:800]
+ alert_handler_reg2hw_alert_cause_mreg_t [15:0] alert_cause; // [799:784]
alert_handler_reg2hw_loc_alert_en_mreg_t [3:0] loc_alert_en; // [783:780]
alert_handler_reg2hw_loc_alert_class_mreg_t [3:0] loc_alert_class; // [779:772]
alert_handler_reg2hw_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [771:768]
@@ -503,8 +503,8 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- alert_handler_hw2reg_intr_state_reg_t intr_state; // [255:252]
- alert_handler_hw2reg_alert_cause_mreg_t [13:0] alert_cause; // [251:224]
+ alert_handler_hw2reg_intr_state_reg_t intr_state; // [259:256]
+ alert_handler_hw2reg_alert_cause_mreg_t [15:0] alert_cause; // [255:224]
alert_handler_hw2reg_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [223:216]
alert_handler_hw2reg_classa_clren_reg_t classa_clren; // [215:216]
alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [215:216]
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index 38c7628..dbef3a6 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -151,6 +151,12 @@
logic alert_en_en_a_13_qs;
logic alert_en_en_a_13_wd;
logic alert_en_en_a_13_we;
+ logic alert_en_en_a_14_qs;
+ logic alert_en_en_a_14_wd;
+ logic alert_en_en_a_14_we;
+ logic alert_en_en_a_15_qs;
+ logic alert_en_en_a_15_wd;
+ logic alert_en_en_a_15_we;
logic [1:0] alert_class_class_a_0_qs;
logic [1:0] alert_class_class_a_0_wd;
logic alert_class_class_a_0_we;
@@ -193,6 +199,12 @@
logic [1:0] alert_class_class_a_13_qs;
logic [1:0] alert_class_class_a_13_wd;
logic alert_class_class_a_13_we;
+ logic [1:0] alert_class_class_a_14_qs;
+ logic [1:0] alert_class_class_a_14_wd;
+ logic alert_class_class_a_14_we;
+ logic [1:0] alert_class_class_a_15_qs;
+ logic [1:0] alert_class_class_a_15_wd;
+ logic alert_class_class_a_15_we;
logic alert_cause_a_0_qs;
logic alert_cause_a_0_wd;
logic alert_cause_a_0_we;
@@ -235,6 +247,12 @@
logic alert_cause_a_13_qs;
logic alert_cause_a_13_wd;
logic alert_cause_a_13_we;
+ logic alert_cause_a_14_qs;
+ logic alert_cause_a_14_wd;
+ logic alert_cause_a_14_we;
+ logic alert_cause_a_15_qs;
+ logic alert_cause_a_15_wd;
+ logic alert_cause_a_15_we;
logic loc_alert_en_en_la_0_qs;
logic loc_alert_en_en_la_0_wd;
logic loc_alert_en_en_la_0_we;
@@ -1205,6 +1223,58 @@
);
+ // F[en_a_14]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_en_a_14 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_en_en_a_14_we & regen_qs),
+ .wd (alert_en_en_a_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en[14].q ),
+
+ // to register interface (read)
+ .qs (alert_en_en_a_14_qs)
+ );
+
+
+ // F[en_a_15]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_en_a_15 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_en_en_a_15_we & regen_qs),
+ .wd (alert_en_en_a_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en[15].q ),
+
+ // to register interface (read)
+ .qs (alert_en_en_a_15_qs)
+ );
+
+
// Subregister 0 of Multireg alert_class
@@ -1574,6 +1644,58 @@
);
+ // F[class_a_14]: 29:28
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_class_a_14 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_class_class_a_14_we & regen_qs),
+ .wd (alert_class_class_a_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class[14].q ),
+
+ // to register interface (read)
+ .qs (alert_class_class_a_14_qs)
+ );
+
+
+ // F[class_a_15]: 31:30
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_class_a_15 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_class_class_a_15_we & regen_qs),
+ .wd (alert_class_class_a_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class[15].q ),
+
+ // to register interface (read)
+ .qs (alert_class_class_a_15_qs)
+ );
+
+
// Subregister 0 of Multireg alert_cause
@@ -1943,6 +2065,58 @@
);
+ // F[a_14]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_a_14 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (alert_cause_a_14_we),
+ .wd (alert_cause_a_14_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[14].de),
+ .d (hw2reg.alert_cause[14].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[14].q ),
+
+ // to register interface (read)
+ .qs (alert_cause_a_14_qs)
+ );
+
+
+ // F[a_15]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_a_15 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (alert_cause_a_15_we),
+ .wd (alert_cause_a_15_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[15].de),
+ .d (hw2reg.alert_cause[15].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[15].q ),
+
+ // to register interface (read)
+ .qs (alert_cause_a_15_qs)
+ );
+
+
// Subregister 0 of Multireg loc_alert_en
@@ -4587,6 +4761,12 @@
assign alert_en_en_a_13_we = addr_hit[5] & reg_we & ~wr_err;
assign alert_en_en_a_13_wd = reg_wdata[13];
+ assign alert_en_en_a_14_we = addr_hit[5] & reg_we & ~wr_err;
+ assign alert_en_en_a_14_wd = reg_wdata[14];
+
+ assign alert_en_en_a_15_we = addr_hit[5] & reg_we & ~wr_err;
+ assign alert_en_en_a_15_wd = reg_wdata[15];
+
assign alert_class_class_a_0_we = addr_hit[6] & reg_we & ~wr_err;
assign alert_class_class_a_0_wd = reg_wdata[1:0];
@@ -4629,6 +4809,12 @@
assign alert_class_class_a_13_we = addr_hit[6] & reg_we & ~wr_err;
assign alert_class_class_a_13_wd = reg_wdata[27:26];
+ assign alert_class_class_a_14_we = addr_hit[6] & reg_we & ~wr_err;
+ assign alert_class_class_a_14_wd = reg_wdata[29:28];
+
+ assign alert_class_class_a_15_we = addr_hit[6] & reg_we & ~wr_err;
+ assign alert_class_class_a_15_wd = reg_wdata[31:30];
+
assign alert_cause_a_0_we = addr_hit[7] & reg_we & ~wr_err;
assign alert_cause_a_0_wd = reg_wdata[0];
@@ -4671,6 +4857,12 @@
assign alert_cause_a_13_we = addr_hit[7] & reg_we & ~wr_err;
assign alert_cause_a_13_wd = reg_wdata[13];
+ assign alert_cause_a_14_we = addr_hit[7] & reg_we & ~wr_err;
+ assign alert_cause_a_14_wd = reg_wdata[14];
+
+ assign alert_cause_a_15_we = addr_hit[7] & reg_we & ~wr_err;
+ assign alert_cause_a_15_wd = reg_wdata[15];
+
assign loc_alert_en_en_la_0_we = addr_hit[8] & reg_we & ~wr_err;
assign loc_alert_en_en_la_0_wd = reg_wdata[0];
@@ -4995,6 +5187,8 @@
reg_rdata_next[11] = alert_en_en_a_11_qs;
reg_rdata_next[12] = alert_en_en_a_12_qs;
reg_rdata_next[13] = alert_en_en_a_13_qs;
+ reg_rdata_next[14] = alert_en_en_a_14_qs;
+ reg_rdata_next[15] = alert_en_en_a_15_qs;
end
addr_hit[6]: begin
@@ -5012,6 +5206,8 @@
reg_rdata_next[23:22] = alert_class_class_a_11_qs;
reg_rdata_next[25:24] = alert_class_class_a_12_qs;
reg_rdata_next[27:26] = alert_class_class_a_13_qs;
+ reg_rdata_next[29:28] = alert_class_class_a_14_qs;
+ reg_rdata_next[31:30] = alert_class_class_a_15_qs;
end
addr_hit[7]: begin
@@ -5029,6 +5225,8 @@
reg_rdata_next[11] = alert_cause_a_11_qs;
reg_rdata_next[12] = alert_cause_a_12_qs;
reg_rdata_next[13] = alert_cause_a_13_qs;
+ reg_rdata_next[14] = alert_cause_a_14_qs;
+ reg_rdata_next[15] = alert_cause_a_15_qs;
end
addr_hit[8]: begin
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
index 3a4156f..eaeb9f2 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -212,6 +212,10 @@
base_addr: 0x40170000
size_byte: 0x11000
}
+ {
+ base_addr: 0x401b0000
+ size_byte: 0x2000
+ }
]
}
{
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
index cba37ef..b7af3cc 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -25,7 +25,8 @@
'{32'h40080000, 32'h40080fff},
'{32'h400a0000, 32'h400c0fff},
'{32'h40150000, 32'h40150fff},
- '{32'h40170000, 32'h40180fff}
+ '{32'h40170000, 32'h40180fff},
+ '{32'h401b0000, 32'h401b1fff}
}},
'{"flash_ctrl", '{
'{32'h40030000, 32'h40030fff}
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
index f9483a6..49eb094 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -10,7 +10,8 @@
localparam logic [31:0] ADDR_SPACE_DEBUG_MEM = 32'h 1a110000;
localparam logic [31:0] ADDR_SPACE_RAM_MAIN = 32'h 10000000;
localparam logic [31:0] ADDR_SPACE_EFLASH = 32'h 20000000;
- localparam logic [5:0][31:0] ADDR_SPACE_PERI = {
+ localparam logic [6:0][31:0] ADDR_SPACE_PERI = {
+ 32'h 401b0000,
32'h 40170000,
32'h 40150000,
32'h 400a0000,
@@ -33,7 +34,8 @@
localparam logic [31:0] ADDR_MASK_DEBUG_MEM = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RAM_MAIN = 32'h 0000ffff;
localparam logic [31:0] ADDR_MASK_EFLASH = 32'h 0007ffff;
- localparam logic [5:0][31:0] ADDR_MASK_PERI = {
+ localparam logic [6:0][31:0] ADDR_MASK_PERI = {
+ 32'h 00001fff,
32'h 00010fff,
32'h 00000fff,
32'h 00020fff,
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
index b697c6d..61ffe89 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -463,7 +463,9 @@
((tl_s1n_23_us_h2d.a_address <= (ADDR_MASK_PERI[4] + ADDR_SPACE_PERI[4])) &&
(tl_s1n_23_us_h2d.a_address >= ADDR_SPACE_PERI[4])) ||
((tl_s1n_23_us_h2d.a_address <= (ADDR_MASK_PERI[5] + ADDR_SPACE_PERI[5])) &&
- (tl_s1n_23_us_h2d.a_address >= ADDR_SPACE_PERI[5]))
+ (tl_s1n_23_us_h2d.a_address >= ADDR_SPACE_PERI[5])) ||
+ ((tl_s1n_23_us_h2d.a_address <= (ADDR_MASK_PERI[6] + ADDR_SPACE_PERI[6])) &&
+ (tl_s1n_23_us_h2d.a_address >= ADDR_SPACE_PERI[6]))
) begin
dev_sel_s1n_23 = 4'd4;
@@ -522,7 +524,9 @@
((tl_s1n_35_us_h2d.a_address <= (ADDR_MASK_PERI[4] + ADDR_SPACE_PERI[4])) &&
(tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_PERI[4])) ||
((tl_s1n_35_us_h2d.a_address <= (ADDR_MASK_PERI[5] + ADDR_SPACE_PERI[5])) &&
- (tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_PERI[5]))
+ (tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_PERI[5])) ||
+ ((tl_s1n_35_us_h2d.a_address <= (ADDR_MASK_PERI[6] + ADDR_SPACE_PERI[6])) &&
+ (tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_PERI[6]))
) begin
dev_sel_s1n_35 = 4'd3;
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index eb23a2b..05c5dec 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -36,6 +36,7 @@
rstmgr
clkmgr
ram_ret
+ otp_ctrl
sensor_ctrl
ast_wrapper
]
@@ -216,6 +217,24 @@
pipeline_byp: "true"
}
{
+ name: otp_ctrl
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: otp_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x401b0000
+ size_byte: 0x2000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
name: sensor_ctrl
type: device
clock: clk_peri_i
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
index 2207535..cc0be5f 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
@@ -75,6 +75,12 @@
}
{ struct: "tl"
type: "req_rsp"
+ name: "tl_otp_ctrl"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
name: "tl_sensor_ctrl"
act: "req"
package: "tlul_pkg"
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
index 6b2a90d..9ab7357 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
@@ -26,5 +26,6 @@
`CONNECT_TL_DEVICE_IF(rstmgr, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(clkmgr, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(ram_ret, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(otp_ctrl, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(sensor_ctrl, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(ast_wrapper, dut, clk_peri_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
index cb7f1a1..f416a54 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -34,6 +34,9 @@
'{"ram_ret", '{
'{32'h18000000, 32'h18000fff}
}},
+ '{"otp_ctrl", '{
+ '{32'h401b0000, 32'h401b1fff}
+ }},
'{"sensor_ctrl", '{
'{32'h40170000, 32'h40170fff}
}},
@@ -53,6 +56,7 @@
"rstmgr",
"clkmgr",
"ram_ret",
+ "otp_ctrl",
"sensor_ctrl",
"ast_wrapper"}}
};
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
index cffe73b..4ed33e5 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -68,6 +68,12 @@
.h2d (tl_ram_ret_o),
.d2h (tl_ram_ret_i)
);
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_otp_ctrl (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_otp_ctrl_o),
+ .d2h (tl_otp_ctrl_i)
+ );
bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sensor_ctrl (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
index b167057..a11a067 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -15,6 +15,7 @@
localparam logic [31:0] ADDR_SPACE_RSTMGR = 32'h 400b0000;
localparam logic [31:0] ADDR_SPACE_CLKMGR = 32'h 400c0000;
localparam logic [31:0] ADDR_SPACE_RAM_RET = 32'h 18000000;
+ localparam logic [31:0] ADDR_SPACE_OTP_CTRL = 32'h 401b0000;
localparam logic [31:0] ADDR_SPACE_SENSOR_CTRL = 32'h 40170000;
localparam logic [31:0] ADDR_SPACE_AST_WRAPPER = 32'h 40180000;
@@ -27,11 +28,12 @@
localparam logic [31:0] ADDR_MASK_RSTMGR = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_CLKMGR = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RAM_RET = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_OTP_CTRL = 32'h 00001fff;
localparam logic [31:0] ADDR_MASK_SENSOR_CTRL = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_AST_WRAPPER = 32'h 00000fff;
localparam int N_HOST = 1;
- localparam int N_DEVICE = 11;
+ localparam int N_DEVICE = 12;
typedef enum int {
TlUart = 0,
@@ -43,8 +45,9 @@
TlRstmgr = 6,
TlClkmgr = 7,
TlRamRet = 8,
- TlSensorCtrl = 9,
- TlAstWrapper = 10
+ TlOtpCtrl = 9,
+ TlSensorCtrl = 10,
+ TlAstWrapper = 11
} tl_device_e;
typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
index d18a8ec..435245c 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -7,7 +7,7 @@
//
// Interconnect
// main
-// -> s1n_12
+// -> s1n_13
// -> uart
// -> gpio
// -> spi_device
@@ -17,6 +17,7 @@
// -> rstmgr
// -> clkmgr
// -> ram_ret
+// -> otp_ctrl
// -> sensor_ctrl
// -> ast_wrapper
@@ -47,6 +48,8 @@
input tlul_pkg::tl_d2h_t tl_clkmgr_i,
output tlul_pkg::tl_h2d_t tl_ram_ret_o,
input tlul_pkg::tl_d2h_t tl_ram_ret_i,
+ output tlul_pkg::tl_h2d_t tl_otp_ctrl_o,
+ input tlul_pkg::tl_d2h_t tl_otp_ctrl_i,
output tlul_pkg::tl_h2d_t tl_sensor_ctrl_o,
input tlul_pkg::tl_d2h_t tl_sensor_ctrl_i,
output tlul_pkg::tl_h2d_t tl_ast_wrapper_o,
@@ -63,89 +66,95 @@
logic unused_scanmode;
assign unused_scanmode = scanmode_i;
- tl_h2d_t tl_s1n_12_us_h2d ;
- tl_d2h_t tl_s1n_12_us_d2h ;
+ tl_h2d_t tl_s1n_13_us_h2d ;
+ tl_d2h_t tl_s1n_13_us_d2h ;
- tl_h2d_t tl_s1n_12_ds_h2d [11];
- tl_d2h_t tl_s1n_12_ds_d2h [11];
+ tl_h2d_t tl_s1n_13_ds_h2d [12];
+ tl_d2h_t tl_s1n_13_ds_d2h [12];
// Create steering signal
- logic [3:0] dev_sel_s1n_12;
+ logic [3:0] dev_sel_s1n_13;
- assign tl_uart_o = tl_s1n_12_ds_h2d[0];
- assign tl_s1n_12_ds_d2h[0] = tl_uart_i;
+ assign tl_uart_o = tl_s1n_13_ds_h2d[0];
+ assign tl_s1n_13_ds_d2h[0] = tl_uart_i;
- assign tl_gpio_o = tl_s1n_12_ds_h2d[1];
- assign tl_s1n_12_ds_d2h[1] = tl_gpio_i;
+ assign tl_gpio_o = tl_s1n_13_ds_h2d[1];
+ assign tl_s1n_13_ds_d2h[1] = tl_gpio_i;
- assign tl_spi_device_o = tl_s1n_12_ds_h2d[2];
- assign tl_s1n_12_ds_d2h[2] = tl_spi_device_i;
+ assign tl_spi_device_o = tl_s1n_13_ds_h2d[2];
+ assign tl_s1n_13_ds_d2h[2] = tl_spi_device_i;
- assign tl_rv_timer_o = tl_s1n_12_ds_h2d[3];
- assign tl_s1n_12_ds_d2h[3] = tl_rv_timer_i;
+ assign tl_rv_timer_o = tl_s1n_13_ds_h2d[3];
+ assign tl_s1n_13_ds_d2h[3] = tl_rv_timer_i;
- assign tl_usbdev_o = tl_s1n_12_ds_h2d[4];
- assign tl_s1n_12_ds_d2h[4] = tl_usbdev_i;
+ assign tl_usbdev_o = tl_s1n_13_ds_h2d[4];
+ assign tl_s1n_13_ds_d2h[4] = tl_usbdev_i;
- assign tl_pwrmgr_o = tl_s1n_12_ds_h2d[5];
- assign tl_s1n_12_ds_d2h[5] = tl_pwrmgr_i;
+ assign tl_pwrmgr_o = tl_s1n_13_ds_h2d[5];
+ assign tl_s1n_13_ds_d2h[5] = tl_pwrmgr_i;
- assign tl_rstmgr_o = tl_s1n_12_ds_h2d[6];
- assign tl_s1n_12_ds_d2h[6] = tl_rstmgr_i;
+ assign tl_rstmgr_o = tl_s1n_13_ds_h2d[6];
+ assign tl_s1n_13_ds_d2h[6] = tl_rstmgr_i;
- assign tl_clkmgr_o = tl_s1n_12_ds_h2d[7];
- assign tl_s1n_12_ds_d2h[7] = tl_clkmgr_i;
+ assign tl_clkmgr_o = tl_s1n_13_ds_h2d[7];
+ assign tl_s1n_13_ds_d2h[7] = tl_clkmgr_i;
- assign tl_ram_ret_o = tl_s1n_12_ds_h2d[8];
- assign tl_s1n_12_ds_d2h[8] = tl_ram_ret_i;
+ assign tl_ram_ret_o = tl_s1n_13_ds_h2d[8];
+ assign tl_s1n_13_ds_d2h[8] = tl_ram_ret_i;
- assign tl_sensor_ctrl_o = tl_s1n_12_ds_h2d[9];
- assign tl_s1n_12_ds_d2h[9] = tl_sensor_ctrl_i;
+ assign tl_otp_ctrl_o = tl_s1n_13_ds_h2d[9];
+ assign tl_s1n_13_ds_d2h[9] = tl_otp_ctrl_i;
- assign tl_ast_wrapper_o = tl_s1n_12_ds_h2d[10];
- assign tl_s1n_12_ds_d2h[10] = tl_ast_wrapper_i;
+ assign tl_sensor_ctrl_o = tl_s1n_13_ds_h2d[10];
+ assign tl_s1n_13_ds_d2h[10] = tl_sensor_ctrl_i;
- assign tl_s1n_12_us_h2d = tl_main_i;
- assign tl_main_o = tl_s1n_12_us_d2h;
+ assign tl_ast_wrapper_o = tl_s1n_13_ds_h2d[11];
+ assign tl_s1n_13_ds_d2h[11] = tl_ast_wrapper_i;
+
+ assign tl_s1n_13_us_h2d = tl_main_i;
+ assign tl_main_o = tl_s1n_13_us_d2h;
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_12 = 4'd11;
- if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
- dev_sel_s1n_12 = 4'd0;
+ dev_sel_s1n_13 = 4'd12;
+ if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
+ dev_sel_s1n_13 = 4'd0;
- end else if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
- dev_sel_s1n_12 = 4'd1;
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+ dev_sel_s1n_13 = 4'd1;
- end else if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
- dev_sel_s1n_12 = 4'd2;
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+ dev_sel_s1n_13 = 4'd2;
- end else if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
- dev_sel_s1n_12 = 4'd3;
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+ dev_sel_s1n_13 = 4'd3;
- end else if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
- dev_sel_s1n_12 = 4'd4;
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
+ dev_sel_s1n_13 = 4'd4;
- end else if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_PWRMGR)) == ADDR_SPACE_PWRMGR) begin
- dev_sel_s1n_12 = 4'd5;
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_PWRMGR)) == ADDR_SPACE_PWRMGR) begin
+ dev_sel_s1n_13 = 4'd5;
- end else if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_RSTMGR)) == ADDR_SPACE_RSTMGR) begin
- dev_sel_s1n_12 = 4'd6;
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_RSTMGR)) == ADDR_SPACE_RSTMGR) begin
+ dev_sel_s1n_13 = 4'd6;
- end else if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_CLKMGR)) == ADDR_SPACE_CLKMGR) begin
- dev_sel_s1n_12 = 4'd7;
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_CLKMGR)) == ADDR_SPACE_CLKMGR) begin
+ dev_sel_s1n_13 = 4'd7;
- end else if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_RAM_RET)) == ADDR_SPACE_RAM_RET) begin
- dev_sel_s1n_12 = 4'd8;
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_RAM_RET)) == ADDR_SPACE_RAM_RET) begin
+ dev_sel_s1n_13 = 4'd8;
- end else if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL)) == ADDR_SPACE_SENSOR_CTRL) begin
- dev_sel_s1n_12 = 4'd9;
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin
+ dev_sel_s1n_13 = 4'd9;
- end else if ((tl_s1n_12_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin
- dev_sel_s1n_12 = 4'd10;
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL)) == ADDR_SPACE_SENSOR_CTRL) begin
+ dev_sel_s1n_13 = 4'd10;
+
+ end else if ((tl_s1n_13_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin
+ dev_sel_s1n_13 = 4'd11;
end
end
@@ -154,17 +163,17 @@
tlul_socket_1n #(
.HReqDepth (4'h0),
.HRspDepth (4'h0),
- .DReqDepth (44'h0),
- .DRspDepth (44'h0),
- .N (11)
- ) u_s1n_12 (
+ .DReqDepth (48'h0),
+ .DRspDepth (48'h0),
+ .N (12)
+ ) u_s1n_13 (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .tl_h_i (tl_s1n_12_us_h2d),
- .tl_h_o (tl_s1n_12_us_d2h),
- .tl_d_o (tl_s1n_12_ds_h2d),
- .tl_d_i (tl_s1n_12_ds_d2h),
- .dev_select_i (dev_sel_s1n_12)
+ .tl_h_i (tl_s1n_13_us_h2d),
+ .tl_h_o (tl_s1n_13_us_d2h),
+ .tl_d_o (tl_s1n_13_ds_h2d),
+ .tl_d_i (tl_s1n_13_ds_d2h),
+ .dev_select_i (dev_sel_s1n_13)
);
endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 6d7de54..9106b73 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -56,6 +56,8 @@
output logic usbdev_usb_ref_pulse_o,
output tlul_pkg::tl_h2d_t ast_tl_req_o,
input tlul_pkg::tl_d2h_t ast_tl_rsp_i,
+ output otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq_o,
+ input otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h_i,
output clkmgr_pkg::clkmgr_ast_out_t clks_ast_o,
output rstmgr_pkg::rstmgr_ast_out_t rsts_ast_o,
input scan_rst_ni, // reset used for test mode
@@ -134,6 +136,7 @@
logic cio_usbdev_dn_en_d2p;
// sensor_ctrl
// keymgr
+ // otp_ctrl
// otbn
@@ -190,6 +193,8 @@
logic intr_usbdev_connected;
logic intr_keymgr_op_done;
logic intr_keymgr_err;
+ logic intr_otp_ctrl_otp_operation_done;
+ logic intr_otp_ctrl_otp_error;
logic intr_otbn_done;
logic intr_otbn_err;
@@ -271,6 +276,8 @@
tlul_pkg::tl_d2h_t clkmgr_tl_rsp;
tlul_pkg::tl_h2d_t ram_ret_tl_req;
tlul_pkg::tl_d2h_t ram_ret_tl_rsp;
+ tlul_pkg::tl_h2d_t otp_ctrl_tl_req;
+ tlul_pkg::tl_d2h_t otp_ctrl_tl_rsp;
tlul_pkg::tl_h2d_t sensor_ctrl_tl_req;
tlul_pkg::tl_d2h_t sensor_ctrl_tl_rsp;
rstmgr_pkg::rstmgr_out_t rstmgr_resets;
@@ -1004,6 +1011,46 @@
.rst_ni (rstmgr_resets.rst_sys_n)
);
+ otp_ctrl u_otp_ctrl (
+
+ // Interrupt
+ .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
+ .intr_otp_error_o (intr_otp_ctrl_otp_error),
+
+ // [11]: otp_fatal_error
+ // [12]: otp_check_failed
+ .alert_tx_o ( alert_tx[12:11] ),
+ .alert_rx_i ( alert_rx[12:11] ),
+
+ // Inter-module signals
+ .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
+ .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i),
+ .otp_edn_o(),
+ .otp_edn_i('0),
+ .pwr_otp_i('0),
+ .pwr_otp_o(),
+ .lc_otp_program_i('0),
+ .lc_otp_program_o(),
+ .lc_otp_token_i('0),
+ .lc_otp_token_o(),
+ .otp_lc_data_o(),
+ .lc_escalate_en_i('0),
+ .lc_provision_en_i('0),
+ .lc_dft_en_i('0),
+ .otp_keymgr_key_o(),
+ .flash_otp_key_i('0),
+ .flash_otp_key_o(),
+ .sram_otp_key_i('0),
+ .sram_otp_key_o(),
+ .otbn_otp_key_i('0),
+ .otbn_otp_key_o(),
+ .hw_cfg_o(),
+ .tl_i(otp_ctrl_tl_req),
+ .tl_o(otp_ctrl_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_io_div4_timers),
+ .rst_ni (rstmgr_resets.rst_sys_io_div4_n)
+ );
+
otbn #(
.RegFile(OtbnRegFile)
) u_otbn (
@@ -1012,11 +1059,11 @@
.intr_done_o (intr_otbn_done),
.intr_err_o (intr_otbn_err),
- // [11]: imem_uncorrectable
- // [12]: dmem_uncorrectable
- // [13]: reg_uncorrectable
- .alert_tx_o ( alert_tx[13:11] ),
- .alert_rx_i ( alert_rx[13:11] ),
+ // [13]: imem_uncorrectable
+ // [14]: dmem_uncorrectable
+ // [15]: reg_uncorrectable
+ .alert_tx_o ( alert_tx[15:13] ),
+ .alert_rx_i ( alert_rx[15:13] ),
// Inter-module signals
.idle_o(clkmgr_idle[2]),
@@ -1209,6 +1256,10 @@
.tl_ram_ret_o(ram_ret_tl_req),
.tl_ram_ret_i(ram_ret_tl_rsp),
+ // port: tl_otp_ctrl
+ .tl_otp_ctrl_o(otp_ctrl_tl_req),
+ .tl_otp_ctrl_i(otp_ctrl_tl_rsp),
+
// port: tl_sensor_ctrl
.tl_sensor_ctrl_o(sensor_ctrl_tl_req),
.tl_sensor_ctrl_i(sensor_ctrl_tl_rsp),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index 36688a4..a701200 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -23,6 +23,7 @@
parameter logic [31:0] TOP_EARLGREY_USBDEV_BASE_ADDR = 32'h40150000;
parameter logic [31:0] TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR = 32'h40170000;
parameter logic [31:0] TOP_EARLGREY_KEYMGR_BASE_ADDR = 32'h401a0000;
+ parameter logic [31:0] TOP_EARLGREY_OTP_CTRL_BASE_ADDR = 32'h401b0000;
parameter logic [31:0] TOP_EARLGREY_OTBN_BASE_ADDR = 32'h50000000;
// Enumeration for DIO pins.
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index 186bdc4..2eeb4e3 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -106,7 +106,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[14] = {
+ top_earlgrey_alert_for_peripheral[16] = {
[kTopEarlgreyAlertIdAesCtrlErrUpdate] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdAesCtrlErrStorage] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdHmacMsgPushShaDisabled] = kTopEarlgreyAlertPeripheralHmac,
@@ -121,5 +121,7 @@
[kTopEarlgreyAlertIdSensorCtrlAstAlerts5] = kTopEarlgreyAlertPeripheralSensorCtrl,
[kTopEarlgreyAlertIdSensorCtrlAstAlerts6] = kTopEarlgreyAlertPeripheralSensorCtrl,
[kTopEarlgreyAlertIdKeymgrErr] = kTopEarlgreyAlertPeripheralKeymgr,
+ [kTopEarlgreyAlertIdOtpCtrlOtpFatalError] = kTopEarlgreyAlertPeripheralOtpCtrl,
+ [kTopEarlgreyAlertIdOtpCtrlOtpCheckFailed] = kTopEarlgreyAlertPeripheralOtpCtrl,
};
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index c325486..7d125d2 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -351,6 +351,24 @@
#define TOP_EARLGREY_KEYMGR_SIZE_BYTES 0x1000u
/**
+ * Peripheral base address for otp_ctrl in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_OTP_CTRL_BASE_ADDR 0x401b0000u
+
+/**
+ * Peripheral size for otp_ctrl in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_OTP_CTRL_BASE_ADDR and
+ * `TOP_EARLGREY_OTP_CTRL_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_OTP_CTRL_SIZE_BYTES 0x2000u
+
+/**
* Peripheral base address for otbn in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -558,7 +576,8 @@
kTopEarlgreyAlertPeripheralOtbn = 2, /**< otbn */
kTopEarlgreyAlertPeripheralSensorCtrl = 3, /**< sensor_ctrl */
kTopEarlgreyAlertPeripheralKeymgr = 4, /**< keymgr */
- kTopEarlgreyAlertPeripheralLast = 4, /**< \internal Final Alert peripheral */
+ kTopEarlgreyAlertPeripheralOtpCtrl = 5, /**< otp_ctrl */
+ kTopEarlgreyAlertPeripheralLast = 5, /**< \internal Final Alert peripheral */
} top_earlgrey_alert_peripheral_t;
/**
@@ -582,7 +601,9 @@
kTopEarlgreyAlertIdSensorCtrlAstAlerts5 = 11, /**< sensor_ctrl_ast_alerts 5 */
kTopEarlgreyAlertIdSensorCtrlAstAlerts6 = 12, /**< sensor_ctrl_ast_alerts 6 */
kTopEarlgreyAlertIdKeymgrErr = 13, /**< keymgr_err */
- kTopEarlgreyAlertIdLast = 13, /**< \internal The Last Valid Alert ID. */
+ kTopEarlgreyAlertIdOtpCtrlOtpFatalError = 14, /**< otp_ctrl_otp_fatal_error */
+ kTopEarlgreyAlertIdOtpCtrlOtpCheckFailed = 15, /**< otp_ctrl_otp_check_failed */
+ kTopEarlgreyAlertIdLast = 15, /**< \internal The Last Valid Alert ID. */
} top_earlgrey_alert_id_t;
/**
@@ -592,7 +613,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
extern const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[14];
+ top_earlgrey_alert_for_peripheral[16];
#define PINMUX_PERIPH_INSEL_IDX_OFFSET 2
