commit a2b79fb3bf31a7a1733d8c6c67660971edca95d5
author Srikrishna Iyer <sriyer@google.com> Fri Jul 31 14:09:53 2020 -0700
committer sriyerg <46467186+sriyerg@users.noreply.github.com> Fri Jul 31 16:57:19 2020 -0700
tree f37a5ea28fdcfffb72e958506da6de15be1713e5
parent 7897d35303dc5b8c3519cd069a8773bd62defa52

[dv] reorg pwrmgr bind & add CSR asserts

Signed-off-by: Srikrishna Iyer <sriyer@google.com>

hw/ip/pwrmgr/dv/sva/pwrmgr_bind.sv

diff --git a/hw/ip/pwrmgr/dv/tb/pwrmgr_bind.sv b/hw/ip/pwrmgr/dv/sva/pwrmgr_bind.sv
similarity index 62%
rename from hw/ip/pwrmgr/dv/tb/pwrmgr_bind.sv
rename to hw/ip/pwrmgr/dv/sva/pwrmgr_bind.sv
index fe57be2..df7dfa1 100644
--- a/hw/ip/pwrmgr/dv/tb/pwrmgr_bind.sv
+++ b/hw/ip/pwrmgr/dv/sva/pwrmgr_bind.sv
@@ -13,4 +13,14 @@
     .d2h  (tl_o)
   );
 
+  import pwrmgr_reg_pkg::*;
+  bind pwrmgr pwrmgr_csr_assert_fpv pwrmgr_csr_assert (
+    .clk_i,
+    .rst_ni,
+    .h2d    (tl_i),
+    .d2h    (tl_o),
+    .reg2hw (reg2hw),
+    .hw2reg (hw2reg)
+  );
+
 endmodule

hw/ip/pwrmgr/dv/sva/pwrmgr_sva.core

diff --git a/hw/ip/pwrmgr/dv/sva/pwrmgr_sva.core b/hw/ip/pwrmgr/dv/sva/pwrmgr_sva.core
new file mode 100644
index 0000000..719052e
--- /dev/null
+++ b/hw/ip/pwrmgr/dv/sva/pwrmgr_sva.core
@@ -0,0 +1,28 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:pwrmgr_sva:0.1"
+description: "PWRMGR assertion modules and bind file."
+filesets:
+  files_dv:
+    depend:
+      - lowrisc:tlul:headers
+      - lowrisc:fpv:csr_assert_gen
+    files:
+      - pwrmgr_bind.sv
+    file_type: systemVerilogSource
+
+generate:
+  csr_assert_gen:
+    generator: csr_assert_gen
+    parameters:
+      spec: ../../data/pwrmgr.hjson
+      depend: lowrisc:ip:pwrmgr_only_reg
+
+targets:
+  default:
+    filesets:
+      - files_dv
+    generate:
+      - csr_assert_gen