| commit | a6d83bfff58888d2df18f91ac5a8e388f3dadfde | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Mon Mar 29 17:02:06 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Wed Mar 31 11:17:22 2021 +0100 |
| tree | b2d885b1fe98e48a6af1d361d60010d4fb0d3919 | |
| parent | 69e88d02bc2951a38becd98a15d7f1a50309f2bd [diff] |
[aon_timer,dv] Wire up interfaces Also rename "clk_aon_rst_vif" to "aon_clk_rst_vif": since it's a (virtual) clock and reset interface with an "aon" flavour, the "aon" part shouldn't come between "clk" and "rst". Also, drive lc_cpu_en_i and sleep_mode_i properly, setting them to something valid from the start of time. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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