[spi_device] BUSY logic update

After discussions, it is decided to use CS# as a clock source then latch
the BUSY @ SCK at the positive edge of CS#. The latched BUSY status will
then block the passthrough logic (and upload logic in following
commits).

The BUSY clear logic has been changed too. BUSY is cleared at the SCK
domain. The FW request is synchronized through pulse synchronizer into
SCK domain then the clear request clears BUSY to 0.

The justification is that the BUSY (and also other STATUS registers)
does not have to be propagated into SCK domain as fast as possible. One
or two clock delay may introduce one more command request from the host
system. But, the implementation is much safer as no uncertainty gap
between the CS# assertion and the latch of BUSY (from SW request).

Other stauts register bits now just go through 2FF synchronizer. The SW
request is stored into SYS clock domain then Status logic will use 2FF
synced version of the bits. This eliminates the use of CS# assertion/
deassertion pulses.

The reconvergence issue won't cause any undesired behavior here. The
values are sent to the host system bit-by-bit. There's chance that old
status bits are transferred at MSBs and new status bits are transferred
at LSBs though.

Signed-off-by: Eunchan Kim <eunchan@opentitan.org>