[prim/dv] Integrate LFSR TB with dvsim
Signed-off-by: Udi Jonnalagadda <udij@google.com>
diff --git a/hw/ip/prim/dv/prim_lfsr/Makefile b/hw/ip/prim/dv/prim_lfsr/Makefile
deleted file mode 100644
index 7e23f5d..0000000
--- a/hw/ip/prim/dv/prim_lfsr/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-# Entry point test Makefile for building and running tests.
-# These are generic set of option groups that apply to all testbenches.
-# This flow requires the following options to be set:
-# DV_DIR - current dv directory that contains the test Makefile
-# DUT_TOP - top level dut module name
-# TB_TOP - top level tb module name
-# DOTF - .f file used for compilation
-# COMPILE_KEY - compile option set
-# TEST_NAME - name of the test to run - this is supplied on the command line
-DV_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
-COMPILE_KEY ?= default
-
-##########################################################
-# A D D I N D I V I D U A L T E S T S B E L O W #
-##########################################################
-
-ifeq (${TEST_NAME},prim_lfsr_gal_xor)
- export DUT_TOP := prim_lfsr
- export TB_TOP := prim_lfsr_tb
- FUSESOC_CORE := lowrisc:dv:prim_lfsr_sim:0.1
- COMPILE_KEY := gal_xor
-endif
-
-ifeq (${TEST_NAME},prim_lfsr_fib_xnor)
- export DUT_TOP := prim_lfsr
- export TB_TOP := prim_lfsr_tb
- FUSESOC_CORE := lowrisc:dv:prim_lfsr_sim:0.1
- COMPILE_KEY := fib_xnor
-endif
-
-ifeq (${COMPILE_KEY},gal_xor)
- BUILD_OPTS := +define+LFSR_TYPE="\"GAL_XOR\""+MAX_LFSR_DW=28+MIN_LFSR_DW=4
-endif
-
-ifeq (${COMPILE_KEY},fib_xnor)
- BUILD_OPTS := +define+LFSR_TYPE="\"FIB_XNOR\""+MAX_LFSR_DW=28+MIN_LFSR_DW=3
-endif
-
-####################################
-# Include the tool Makefile below #
-# Dont add anything else below it! #
-####################################
-include ${DV_DIR}/../../../../dv/tools/Makefile
diff --git a/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core b/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core
index 83eaf03..2555492 100644
--- a/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core
+++ b/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core
@@ -7,7 +7,7 @@
filesets:
files_rtl:
depend:
- - lowrisc:prim:all
+ - lowrisc:prim:lfsr:0.1
file_type: systemVerilogSource
files_dv:
diff --git a/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson b/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson
new file mode 100644
index 0000000..cdae3e5
--- /dev/null
+++ b/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson
@@ -0,0 +1,61 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // Name of the sim cfg - typically same as the name of the DUT.
+ name: prim_lfsr
+
+ // Top level dut name (sv module).
+ dut: prim_lfsr
+
+ // Top level testbench name (sv module).
+ tb: prim_lfsr_tb
+
+ // Simulator used to sign off this block
+ tool: vcs
+
+ // Fusesoc core file used for building the file list.
+ fusesoc_core: lowrisc:dv:prim_lfsr_sim:0.1
+
+ // Testplan hjson file.
+ testplan: "{proj_root}/hw/ip/prim/dv/prim_lfsr/prim_lfsr_testplan.hjson"
+
+ // Import additional common sim cfg files.
+ import_cfgs: ["{proj_root}/hw/dv/data/common_sim_cfg.hjson"]
+
+ // Default iterations for all tests - each test entry can override this.
+ reseed: 50
+
+ build_modes: [
+ {
+ name: prim_lfsr_dw_8
+ build_opts: ["+define+MAX_LFSR_DW=8"]
+ }
+ {
+ name: prim_lfsr_dw_24
+ build_opts: ["+define+MAX_LFSR_DW=24"]
+ }
+ ]
+
+ // List of test specifications.
+ tests: [
+ {
+ name: prim_lfsr_sanity
+ // limit max lfsr length to reduce private CI runtime.
+ build_mode: prim_lfsr_dw_8
+ }
+ {
+ name: prim_lfsr_basic_test
+ build_mode: prim_lfsr_dw_24
+ }
+ ]
+
+ // List of regressions.
+ regressions: [
+ {
+ name: sanity
+ tests: ["prim_lfsr_sanity"]
+ }
+ ]
+}
+
diff --git a/hw/ip/prim/dv/prim_lfsr/prim_lfsr_testplan.hjson b/hw/ip/prim/dv/prim_lfsr/prim_lfsr_testplan.hjson
new file mode 100644
index 0000000..d828196
--- /dev/null
+++ b/hw/ip/prim/dv/prim_lfsr/prim_lfsr_testplan.hjson
@@ -0,0 +1,16 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "prim_lfsr"
+ import_testplans: []
+ entries: [
+ {
+ name: sanity
+ desc: '''Simple LFSR test - sweep through all implementations within a
+ certain range to check whether they are max length.'''
+ milestone: V2
+ tests: ["prim_lfsr_sanity"]
+ }
+ ]
+}
diff --git a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
index 2e652aa..f06d175 100644
--- a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
+++ b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
@@ -21,6 +21,7 @@
"{proj_root}/hw/ip/uart/dv/uart_sim_cfg.hjson",
"{proj_root}/hw/ip/usbdev/dv/usbdev_sim_cfg.hjson",
"{proj_root}/hw/ip/prim/dv/prim_present/prim_present_sim_cfg.hjson",
+ "{proj_root}/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson",
"{proj_root}/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_sim_cfg.hjson",
"{proj_root}/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson",
"{proj_root}/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson",
