[test] Add rom_e2e_bootstrap_phase2_reset
Fixes #14463
Signed-off-by: Alphan Ulusoy <alphan@google.com>
diff --git a/sw/device/silicon_creator/rom/data/rom_testplan.hjson b/sw/device/silicon_creator/rom/data/rom_testplan.hjson
index 6ce1cec..6a9d226 100644
--- a/sw/device/silicon_creator/rom/data/rom_testplan.hjson
+++ b/sw/device/silicon_creator/rom/data/rom_testplan.hjson
@@ -385,15 +385,13 @@
`OWNER_SW_CFG_ROM_BOOTSTRAP_EN` OTP item must be `kHardenedBoolTrue` (`0x739`).
- - Apply bootstrap pin strapping and reset the chip.
- - Verify that the chip responds to `READ_STATUS` (`0x05`) with `0x00`.
- - Send `CHIP_ERASE` (`0xc7`).
- - This moves bootstrap to phase 2.
+ - For `erase` in {`SECTOR_ERASE` (`0x20`), `CHIP_ERASE` (`0xc7`)}:
+ - Apply bootstrap pin strapping and reset the chip.
+ - Send `erase` transition to phase 2.
- Release pins and send `RESET` (`0x99`).
- - Verify that the chip outputs the expected `BFV`: `0142500d` over UART.
+ - Verify that the chip outputs the expected `BFV`: `0142500d` over UART (`kErrorBootPolicyBadIdentifier`).
- ROM will continously reset the chip and output the same `BFV` and `LCV`.
- - Verify that the chip does not respond to `READ_STATUS` (`0x05`).
- - The data on the CIPO line must be `0xff`.
+ - Verify that the chip does not respond to `READ_SFDP` (`0x5a`).
'''
tags: ["rom", "verilator", "dv", "fpga", "silicon"]
stage: V2
diff --git a/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs b/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs
index 1be8ba1..10b7eaa 100644
--- a/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs
+++ b/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs
@@ -429,6 +429,40 @@
Ok(())
}
+fn test_bootstrap_phase2_reset(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
+ let _bs = BootstrapTest::start(transport, opts.init.bootstrap.options.reset_delay)?;
+
+ let spi = transport.spi("0")?;
+ let uart = transport.uart("0")?;
+ let mut console = UartConsole {
+ timeout: Some(Duration::new(1, 0)),
+ // `kErrorBootPolicyBadIdentifier` (0142500d) is defined in `error.h`.
+ exit_success: Some(Regex::new("BFV:0142500d\r\n")?),
+ ..Default::default()
+ };
+ // Send CHIP_ERASE to transition to phase 2.
+ SpiFlash::from_spi(&*spi)?.chip_erase(&*spi)?;
+ // Remove strapping so that chip fails to boot instead of going into bootstrap.
+ transport.remove_pin_strapping("ROM_BOOTSTRAP")?;
+ // Discard buffered messages before interacting with the console.
+ uart.clear_rx_buffer()?;
+ SpiFlash::chip_reset(&*spi)?;
+ let result = console.interact(&*uart, None, Some(&mut std::io::stdout()))?;
+ if result != ExitStatus::ExitSuccess {
+ bail!("FAIL: {:?}", result);
+ }
+
+ assert!(matches!(
+ SpiFlash::read_sfdp(&*spi)
+ .unwrap_err()
+ .downcast::<sfdp::Error>()
+ .unwrap(),
+ sfdp::Error::WrongHeaderSignature(..)
+ ));
+
+ Ok(())
+}
+
fn main() -> Result<()> {
let opts = Opts::from_args();
opts.init.init_logging();
@@ -453,6 +487,7 @@
execute_test!(test_bootstrap_phase1_erase, &opts, &transport, erase_cmd);
}
execute_test!(test_bootstrap_phase1_read, &opts, &transport);
+ execute_test!(test_bootstrap_phase2_reset, &opts, &transport);
Ok(())
}
