[entropy_src/rtl] symbol-based repetition count health test
An additional symobl-based repetition count health test is added.
Changed the rep counter to initialize to 1, as NIST shows.
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/ip/entropy_src/data/entropy_src.hjson b/hw/ip/entropy_src/data/entropy_src.hjson
index 67e5334..a8161fb 100644
--- a/hw/ip/entropy_src/data/entropy_src.hjson
+++ b/hw/ip/entropy_src/data/entropy_src.hjson
@@ -164,6 +164,12 @@
to ENTROPY_SRC."
'''
}
+ { bits: "13",
+ name: "REPCNTS_DISABLE",
+ desc: '''Setting this bit disables the health test called Repetition Count test,
+ which is based on counting symbols.
+ '''
+ }
]
},
{ name: "RATE",
@@ -277,6 +283,42 @@
}
]
},
+ { name: "REPCNTS_THRESHOLDS",
+ desc: "Repetition count symbol test thresholds register",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ hwext: "true",
+ hwqe: "true",
+ regwen: "REGWEN",
+ tags: [// Exclude from writes to these field because they are one-way updates
+ "excl:CsrAllTests:CsrExclWrite"]
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_THRESH",
+ desc: '''This is the threshold size for the repetition count symbol health test.
+ This value is used in normal mode when entropy is being tested in
+ FIPS/CC compliance mode.
+ This register must be written before the module is enabled.
+ Writing to this register will only update the register if the
+ written value is less than the current value of this register.
+ A read from this register always reflects the current value.
+ '''
+ resval: "0xFFFF"
+ }
+ { bits: "31:16",
+ name: "BYPASS_THRESH",
+ desc: '''This is the threshold size for the repetition count symbol health test
+ running in bypass mode. This mode is active after reset for the
+ first and only test run, or when this mode is programmed by firmware.
+ This register must be written before the module is enabled.
+ Writing to this register will only update the register if the
+ written value is less than the current value of this register.
+ A read from this register always reflects the current value.
+ '''
+ resval: "0xFFFF"
+ }
+ ]
+ },
{ name: "ADAPTP_HI_THRESHOLDS",
desc: "Adaptive proportion test high thresholds register",
swaccess: "rw",
@@ -545,6 +587,22 @@
}
]
},
+ { name: "REPCNTS_HI_WATERMARKS",
+ desc: "Repetition count symbol test high watermarks register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "15:0",
+ name: "FIPS_WATERMARK",
+ desc: "High watermark value of the REPCNTS test in FIPS mode."
+ }
+ { bits: "31:16",
+ name: "BYPASS_WATERMARK",
+ desc: "High watermark value of the REPCNTS test in bypass mode."
+ }
+ ]
+ },
{ name: "ADAPTP_HI_WATERMARKS",
desc: "Adaptive proportion test high watermarks register",
swaccess: "ro",
@@ -677,6 +735,20 @@
}
]
},
+ { name: "REPCNTS_TOTAL_FAILS",
+ desc: "Repetition count symbol test failure counter register",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ name: "REPCNTS_TOTAL_FAILS",
+ desc: '''This register will hold a running count of test failures observed
+ during normal operation. It will persist until cleared.
+ '''
+ }
+ ]
+ },
{ name: "ADAPTP_HI_TOTAL_FAILS",
desc: "Adaptive proportion high test failure counter register",
swaccess: "ro",
@@ -863,6 +935,14 @@
will persist until it is cleared.
'''
}
+ { bits: "31:28",
+ name: "REPCNTS_FAIL_COUNT",
+ desc: '''This field will hold a running count of test failures that
+ contribute to the total alert count. It will be reset after every
+ passing test sequence. If an alert is signaled, this value
+ will persist until it is cleared.
+ '''
+ }
]
},
{ name: "EXTHT_FAIL_COUNTS",
diff --git a/hw/ip/entropy_src/entropy_src.core b/hw/ip/entropy_src/entropy_src.core
index c0659d9..4b95d56 100644
--- a/hw/ip/entropy_src/entropy_src.core
+++ b/hw/ip/entropy_src/entropy_src.core
@@ -23,6 +23,7 @@
- rtl/entropy_src_ack_sm.sv
- rtl/entropy_src_main_sm.sv
- rtl/entropy_src_repcnt_ht.sv
+ - rtl/entropy_src_repcnts_ht.sv
- rtl/entropy_src_adaptp_ht.sv
- rtl/entropy_src_bucket_ht.sv
- rtl/entropy_src_markov_ht.sv
diff --git a/hw/ip/entropy_src/rtl/entropy_src_core.sv b/hw/ip/entropy_src/rtl/entropy_src_core.sv
index bd54a8b..1bacca1 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_core.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_core.sv
@@ -137,6 +137,7 @@
logic [FullRegWidth-1:0] alert_threshold;
logic recov_alert_event;
logic repcnt_active;
+ logic repcnts_active;
logic adaptp_active;
logic bucket_active;
logic markov_active;
@@ -172,6 +173,20 @@
logic [EighthRegWidth-1:0] repcnt_fail_count;
logic repcnt_fail_pulse;
+ logic [HalfRegWidth-1:0] repcnts_fips_threshold;
+ logic [HalfRegWidth-1:0] repcnts_fips_threshold_oneway;
+ logic repcnts_fips_threshold_wr;
+ logic [HalfRegWidth-1:0] repcnts_bypass_threshold;
+ logic [HalfRegWidth-1:0] repcnts_bypass_threshold_oneway;
+ logic repcnts_bypass_threshold_wr;
+ logic [HalfRegWidth-1:0] repcnts_threshold;
+ logic [HalfRegWidth-1:0] repcnts_event_cnt;
+ logic [HalfRegWidth-1:0] repcnts_event_hwm_fips;
+ logic [HalfRegWidth-1:0] repcnts_event_hwm_bypass;
+ logic [FullRegWidth-1:0] repcnts_total_fails;
+ logic [EighthRegWidth-1:0] repcnts_fail_count;
+ logic repcnts_fail_pulse;
+
logic [HalfRegWidth-1:0] adaptp_hi_fips_threshold;
logic [HalfRegWidth-1:0] adaptp_hi_fips_threshold_oneway;
logic adaptp_hi_fips_threshold_wr;
@@ -680,6 +695,7 @@
assign ht_esbus_vld_dly2_d = ht_esbus_vld_dly_q;
assign repcnt_active = !reg2hw.conf.repcnt_disable.q && es_enable;
+ assign repcnts_active = !reg2hw.conf.repcnts_disable.q && es_enable;
assign adaptp_active = !reg2hw.conf.adaptp_disable.q && es_enable;
assign bucket_active = !reg2hw.conf.bucket_disable.q && es_enable;
assign markov_active = !reg2hw.conf.markov_disable.q && es_enable;
@@ -696,6 +712,13 @@
assign repcnt_bypass_threshold_wr = reg2hw.repcnt_thresholds.bypass_thresh.qe;
assign hw2reg.repcnt_thresholds.bypass_thresh.d = repcnt_bypass_threshold_oneway;
+ assign repcnts_fips_threshold = reg2hw.repcnts_thresholds.fips_thresh.q;
+ assign repcnts_fips_threshold_wr = reg2hw.repcnts_thresholds.fips_thresh.qe;
+ assign hw2reg.repcnts_thresholds.fips_thresh.d = repcnts_fips_threshold_oneway;
+ assign repcnts_bypass_threshold = reg2hw.repcnts_thresholds.bypass_thresh.q;
+ assign repcnts_bypass_threshold_wr = reg2hw.repcnts_thresholds.bypass_thresh.qe;
+ assign hw2reg.repcnts_thresholds.bypass_thresh.d = repcnts_bypass_threshold_oneway;
+
assign adaptp_hi_fips_threshold = reg2hw.adaptp_hi_thresholds.fips_thresh.q;
assign adaptp_hi_fips_threshold_wr = reg2hw.adaptp_hi_thresholds.fips_thresh.qe;
@@ -785,6 +808,38 @@
.value_o (repcnt_bypass_threshold_oneway)
);
+ //------------------------------
+ // repcnts one-way thresholds
+ //------------------------------
+ assign repcnts_threshold = es_bypass_mode ? repcnts_bypass_threshold_oneway :
+ repcnts_fips_threshold_oneway;
+
+ entropy_src_watermark_reg #(
+ .RegWidth(HalfRegWidth),
+ .HighWatermark(0)
+ ) u_entropy_src_watermark_reg_repcnts_thresh_fips (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (1'b0),
+ .active_i (!es_enable),
+ .event_i (repcnts_fips_threshold_wr),
+ .value_i (repcnts_fips_threshold),
+ .value_o (repcnts_fips_threshold_oneway)
+ );
+
+ entropy_src_watermark_reg #(
+ .RegWidth(HalfRegWidth),
+ .HighWatermark(0)
+ ) u_entropy_src_watermark_reg_repcnts_thresh_bypass (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (1'b0),
+ .active_i (!es_enable),
+ .event_i (repcnts_bypass_threshold_wr),
+ .value_i (repcnts_bypass_threshold),
+ .value_o (repcnts_bypass_threshold_oneway)
+ );
+
//------------------------------
// adaptp one-way thresholds
@@ -1102,6 +1157,66 @@
assign hw2reg.repcnt_total_fails.d = repcnt_total_fails;
//--------------------------------------------
+ // repetitive count symbol test
+ //--------------------------------------------
+
+ entropy_src_repcnts_ht #(
+ .RegWidth(HalfRegWidth),
+ .RngBusWidth(RngBusWidth)
+ ) u_entropy_src_repcnts_ht (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .entropy_bit_i (health_test_esbus),
+ .entropy_bit_vld_i (health_test_esbus_vld),
+ .clear_i (health_test_clr),
+ .active_i (repcnts_active),
+ .thresh_i (repcnts_threshold),
+ .test_cnt_o (repcnts_event_cnt),
+ .test_fail_pulse_o (repcnts_fail_pulse)
+ );
+
+ entropy_src_watermark_reg #(
+ .RegWidth(HalfRegWidth),
+ .HighWatermark(1)
+ ) u_entropy_src_watermark_reg_repcnts_fips (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (repcnts_active),
+ .event_i (repcnts_fail_pulse && !es_bypass_mode),
+ .value_i (repcnts_event_cnt),
+ .value_o (repcnts_event_hwm_fips)
+ );
+
+ entropy_src_watermark_reg #(
+ .RegWidth(HalfRegWidth),
+ .HighWatermark(1)
+ ) u_entropy_src_watermark_reg_repcnts_bypass (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (repcnts_active),
+ .event_i (repcnts_fail_pulse && es_bypass_mode),
+ .value_i (repcnts_event_cnt),
+ .value_o (repcnts_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg #(
+ .RegWidth(FullRegWidth)
+ ) u_entropy_src_cntr_reg_repcnts (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (repcnts_active),
+ .event_i (repcnts_fail_pulse),
+ .value_o (repcnts_total_fails)
+ );
+
+ assign hw2reg.repcnts_hi_watermarks.fips_watermark.d = repcnts_event_hwm_fips;
+ assign hw2reg.repcnts_hi_watermarks.bypass_watermark.d = repcnts_event_hwm_bypass;
+ assign hw2reg.repcnts_total_fails.d = repcnts_total_fails;
+
+ //--------------------------------------------
// adaptive proportion test
//--------------------------------------------
@@ -1499,11 +1614,12 @@
.value_o (any_fail_count)
);
- assign any_active = repcnt_active || adaptp_active ||
+ assign any_active = repcnt_active || repcnts_active || adaptp_active ||
bucket_active || markov_active || extht_active;
assign any_fail_pulse =
repcnt_fail_pulse ||
+ repcnts_fail_pulse ||
adaptp_hi_fail_pulse || adaptp_lo_fail_pulse ||
bucket_fail_pulse ||
markov_hi_fail_pulse ||markov_lo_fail_pulse ||
@@ -1537,6 +1653,20 @@
assign hw2reg.alert_fail_counts.repcnt_fail_count.d = repcnt_fail_count;
+ // repcnts fail counter
+ entropy_src_cntr_reg #(
+ .RegWidth(EighthRegWidth)
+ ) u_entropy_src_cntr_reg_repcnts_alert_fails (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (repcnts_active),
+ .event_i (repcnts_fail_pulse),
+ .value_o (repcnts_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.repcnts_fail_count.d = repcnts_fail_count;
+
// adaptp fail counter hi and lo
entropy_src_cntr_reg #(
.RegWidth(EighthRegWidth)
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
index d5b10fb..4b5de6f 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
@@ -101,6 +101,9 @@
struct packed {
logic q;
} extht_enable;
+ struct packed {
+ logic q;
+ } repcnts_disable;
} entropy_src_reg2hw_conf_reg_t;
typedef struct packed {
@@ -150,6 +153,17 @@
logic [15:0] q;
logic qe;
} bypass_thresh;
+ } entropy_src_reg2hw_repcnts_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] q;
+ logic qe;
+ } fips_thresh;
+ struct packed {
+ logic [15:0] q;
+ logic qe;
+ } bypass_thresh;
} entropy_src_reg2hw_adaptp_hi_thresholds_reg_t;
typedef struct packed {
@@ -292,6 +306,15 @@
struct packed {
logic [15:0] d;
} bypass_thresh;
+ } entropy_src_hw2reg_repcnts_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] d;
+ } fips_thresh;
+ struct packed {
+ logic [15:0] d;
+ } bypass_thresh;
} entropy_src_hw2reg_adaptp_hi_thresholds_reg_t;
typedef struct packed {
@@ -364,6 +387,15 @@
struct packed {
logic [15:0] d;
} bypass_watermark;
+ } entropy_src_hw2reg_repcnts_hi_watermarks_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] d;
+ } fips_watermark;
+ struct packed {
+ logic [15:0] d;
+ } bypass_watermark;
} entropy_src_hw2reg_adaptp_hi_watermarks_reg_t;
typedef struct packed {
@@ -426,6 +458,10 @@
typedef struct packed {
logic [31:0] d;
+ } entropy_src_hw2reg_repcnts_total_fails_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
} entropy_src_hw2reg_adaptp_hi_total_fails_reg_t;
typedef struct packed {
@@ -475,6 +511,9 @@
struct packed {
logic [3:0] d;
} markov_lo_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } repcnts_fail_count;
} entropy_src_hw2reg_alert_fail_counts_reg_t;
typedef struct packed {
@@ -555,17 +594,18 @@
// Register -> HW type
typedef struct packed {
- entropy_src_reg2hw_intr_state_reg_t intr_state; // [501:499]
- entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [498:496]
- entropy_src_reg2hw_intr_test_reg_t intr_test; // [495:490]
- entropy_src_reg2hw_alert_test_reg_t alert_test; // [489:486]
- entropy_src_reg2hw_regwen_reg_t regwen; // [485:485]
- entropy_src_reg2hw_conf_reg_t conf; // [484:473]
- entropy_src_reg2hw_rate_reg_t rate; // [472:457]
- entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [456:455]
- entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [454:422]
- entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [421:390]
- entropy_src_reg2hw_repcnt_thresholds_reg_t repcnt_thresholds; // [389:356]
+ entropy_src_reg2hw_intr_state_reg_t intr_state; // [536:534]
+ entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [533:531]
+ entropy_src_reg2hw_intr_test_reg_t intr_test; // [530:525]
+ entropy_src_reg2hw_alert_test_reg_t alert_test; // [524:521]
+ entropy_src_reg2hw_regwen_reg_t regwen; // [520:520]
+ entropy_src_reg2hw_conf_reg_t conf; // [519:507]
+ entropy_src_reg2hw_rate_reg_t rate; // [506:491]
+ entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [490:489]
+ entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [488:456]
+ entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [455:424]
+ entropy_src_reg2hw_repcnt_thresholds_reg_t repcnt_thresholds; // [423:390]
+ entropy_src_reg2hw_repcnts_thresholds_reg_t repcnts_thresholds; // [389:356]
entropy_src_reg2hw_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [355:322]
entropy_src_reg2hw_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [321:288]
entropy_src_reg2hw_bucket_thresholds_reg_t bucket_thresholds; // [287:254]
@@ -584,34 +624,37 @@
// HW -> register type
typedef struct packed {
- entropy_src_hw2reg_intr_state_reg_t intr_state; // [935:930]
- entropy_src_hw2reg_entropy_data_reg_t entropy_data; // [929:898]
- entropy_src_hw2reg_repcnt_thresholds_reg_t repcnt_thresholds; // [897:866]
- entropy_src_hw2reg_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [865:834]
- entropy_src_hw2reg_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [833:802]
- entropy_src_hw2reg_bucket_thresholds_reg_t bucket_thresholds; // [801:770]
- entropy_src_hw2reg_markov_hi_thresholds_reg_t markov_hi_thresholds; // [769:738]
- entropy_src_hw2reg_markov_lo_thresholds_reg_t markov_lo_thresholds; // [737:706]
- entropy_src_hw2reg_extht_hi_thresholds_reg_t extht_hi_thresholds; // [705:674]
- entropy_src_hw2reg_extht_lo_thresholds_reg_t extht_lo_thresholds; // [673:642]
- entropy_src_hw2reg_repcnt_hi_watermarks_reg_t repcnt_hi_watermarks; // [641:610]
- entropy_src_hw2reg_adaptp_hi_watermarks_reg_t adaptp_hi_watermarks; // [609:578]
- entropy_src_hw2reg_adaptp_lo_watermarks_reg_t adaptp_lo_watermarks; // [577:546]
- entropy_src_hw2reg_extht_hi_watermarks_reg_t extht_hi_watermarks; // [545:514]
- entropy_src_hw2reg_extht_lo_watermarks_reg_t extht_lo_watermarks; // [513:482]
- entropy_src_hw2reg_bucket_hi_watermarks_reg_t bucket_hi_watermarks; // [481:450]
- entropy_src_hw2reg_markov_hi_watermarks_reg_t markov_hi_watermarks; // [449:418]
- entropy_src_hw2reg_markov_lo_watermarks_reg_t markov_lo_watermarks; // [417:386]
- entropy_src_hw2reg_repcnt_total_fails_reg_t repcnt_total_fails; // [385:354]
- entropy_src_hw2reg_adaptp_hi_total_fails_reg_t adaptp_hi_total_fails; // [353:322]
- entropy_src_hw2reg_adaptp_lo_total_fails_reg_t adaptp_lo_total_fails; // [321:290]
- entropy_src_hw2reg_bucket_total_fails_reg_t bucket_total_fails; // [289:258]
- entropy_src_hw2reg_markov_hi_total_fails_reg_t markov_hi_total_fails; // [257:226]
- entropy_src_hw2reg_markov_lo_total_fails_reg_t markov_lo_total_fails; // [225:194]
- entropy_src_hw2reg_extht_hi_total_fails_reg_t extht_hi_total_fails; // [193:162]
- entropy_src_hw2reg_extht_lo_total_fails_reg_t extht_lo_total_fails; // [161:130]
- entropy_src_hw2reg_alert_summary_fail_counts_reg_t alert_summary_fail_counts; // [129:98]
- entropy_src_hw2reg_alert_fail_counts_reg_t alert_fail_counts; // [97:74]
+ entropy_src_hw2reg_intr_state_reg_t intr_state; // [1035:1030]
+ entropy_src_hw2reg_entropy_data_reg_t entropy_data; // [1029:998]
+ entropy_src_hw2reg_repcnt_thresholds_reg_t repcnt_thresholds; // [997:966]
+ entropy_src_hw2reg_repcnts_thresholds_reg_t repcnts_thresholds; // [965:934]
+ entropy_src_hw2reg_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [933:902]
+ entropy_src_hw2reg_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [901:870]
+ entropy_src_hw2reg_bucket_thresholds_reg_t bucket_thresholds; // [869:838]
+ entropy_src_hw2reg_markov_hi_thresholds_reg_t markov_hi_thresholds; // [837:806]
+ entropy_src_hw2reg_markov_lo_thresholds_reg_t markov_lo_thresholds; // [805:774]
+ entropy_src_hw2reg_extht_hi_thresholds_reg_t extht_hi_thresholds; // [773:742]
+ entropy_src_hw2reg_extht_lo_thresholds_reg_t extht_lo_thresholds; // [741:710]
+ entropy_src_hw2reg_repcnt_hi_watermarks_reg_t repcnt_hi_watermarks; // [709:678]
+ entropy_src_hw2reg_repcnts_hi_watermarks_reg_t repcnts_hi_watermarks; // [677:646]
+ entropy_src_hw2reg_adaptp_hi_watermarks_reg_t adaptp_hi_watermarks; // [645:614]
+ entropy_src_hw2reg_adaptp_lo_watermarks_reg_t adaptp_lo_watermarks; // [613:582]
+ entropy_src_hw2reg_extht_hi_watermarks_reg_t extht_hi_watermarks; // [581:550]
+ entropy_src_hw2reg_extht_lo_watermarks_reg_t extht_lo_watermarks; // [549:518]
+ entropy_src_hw2reg_bucket_hi_watermarks_reg_t bucket_hi_watermarks; // [517:486]
+ entropy_src_hw2reg_markov_hi_watermarks_reg_t markov_hi_watermarks; // [485:454]
+ entropy_src_hw2reg_markov_lo_watermarks_reg_t markov_lo_watermarks; // [453:422]
+ entropy_src_hw2reg_repcnt_total_fails_reg_t repcnt_total_fails; // [421:390]
+ entropy_src_hw2reg_repcnts_total_fails_reg_t repcnts_total_fails; // [389:358]
+ entropy_src_hw2reg_adaptp_hi_total_fails_reg_t adaptp_hi_total_fails; // [357:326]
+ entropy_src_hw2reg_adaptp_lo_total_fails_reg_t adaptp_lo_total_fails; // [325:294]
+ entropy_src_hw2reg_bucket_total_fails_reg_t bucket_total_fails; // [293:262]
+ entropy_src_hw2reg_markov_hi_total_fails_reg_t markov_hi_total_fails; // [261:230]
+ entropy_src_hw2reg_markov_lo_total_fails_reg_t markov_lo_total_fails; // [229:198]
+ entropy_src_hw2reg_extht_hi_total_fails_reg_t extht_hi_total_fails; // [197:166]
+ entropy_src_hw2reg_extht_lo_total_fails_reg_t extht_lo_total_fails; // [165:134]
+ entropy_src_hw2reg_alert_summary_fail_counts_reg_t alert_summary_fail_counts; // [133:102]
+ entropy_src_hw2reg_alert_fail_counts_reg_t alert_fail_counts; // [101:74]
entropy_src_hw2reg_extht_fail_counts_reg_t extht_fail_counts; // [73:66]
entropy_src_hw2reg_fw_ov_rd_data_reg_t fw_ov_rd_data; // [65:34]
entropy_src_hw2reg_fw_ov_fifo_sts_reg_t fw_ov_fifo_sts; // [33:27]
@@ -632,42 +675,45 @@
parameter logic [BlockAw-1:0] ENTROPY_SRC_ENTROPY_DATA_OFFSET = 8'h 24;
parameter logic [BlockAw-1:0] ENTROPY_SRC_HEALTH_TEST_WINDOWS_OFFSET = 8'h 28;
parameter logic [BlockAw-1:0] ENTROPY_SRC_REPCNT_THRESHOLDS_OFFSET = 8'h 2c;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET = 8'h 30;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET = 8'h 34;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET = 8'h 38;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_HI_THRESHOLDS_OFFSET = 8'h 3c;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_LO_THRESHOLDS_OFFSET = 8'h 40;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_HI_THRESHOLDS_OFFSET = 8'h 44;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_LO_THRESHOLDS_OFFSET = 8'h 48;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET = 8'h 4c;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET = 8'h 50;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET = 8'h 54;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_HI_WATERMARKS_OFFSET = 8'h 58;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_LO_WATERMARKS_OFFSET = 8'h 5c;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET = 8'h 60;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET = 8'h 64;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_LO_WATERMARKS_OFFSET = 8'h 68;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET = 8'h 6c;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET = 8'h 70;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET = 8'h 74;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET = 8'h 78;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_OFFSET = 8'h 7c;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_OFFSET = 8'h 80;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_OFFSET = 8'h 84;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_OFFSET = 8'h 88;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ALERT_THRESHOLD_OFFSET = 8'h 8c;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_OFFSET = 8'h 90;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET = 8'h 94;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_FAIL_COUNTS_OFFSET = 8'h 98;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_FW_OV_CONTROL_OFFSET = 8'h 9c;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_FW_OV_RD_DATA_OFFSET = 8'h a0;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_FW_OV_WR_DATA_OFFSET = 8'h a4;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_FW_OV_FIFO_STS_OFFSET = 8'h a8;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_PRE_COND_FIFO_DEPTH_OFFSET = 8'h ac;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_DEBUG_STATUS_OFFSET = 8'h b0;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_SEED_OFFSET = 8'h b4;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ERR_CODE_OFFSET = 8'h b8;
- parameter logic [BlockAw-1:0] ENTROPY_SRC_ERR_CODE_TEST_OFFSET = 8'h bc;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_REPCNTS_THRESHOLDS_OFFSET = 8'h 30;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET = 8'h 34;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET = 8'h 38;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET = 8'h 3c;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_HI_THRESHOLDS_OFFSET = 8'h 40;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_LO_THRESHOLDS_OFFSET = 8'h 44;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_HI_THRESHOLDS_OFFSET = 8'h 48;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_LO_THRESHOLDS_OFFSET = 8'h 4c;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET = 8'h 50;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_REPCNTS_HI_WATERMARKS_OFFSET = 8'h 54;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET = 8'h 58;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET = 8'h 5c;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_HI_WATERMARKS_OFFSET = 8'h 60;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_LO_WATERMARKS_OFFSET = 8'h 64;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET = 8'h 68;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET = 8'h 6c;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_LO_WATERMARKS_OFFSET = 8'h 70;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET = 8'h 74;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_REPCNTS_TOTAL_FAILS_OFFSET = 8'h 78;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET = 8'h 7c;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET = 8'h 80;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET = 8'h 84;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_OFFSET = 8'h 88;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_OFFSET = 8'h 8c;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_OFFSET = 8'h 90;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_OFFSET = 8'h 94;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ALERT_THRESHOLD_OFFSET = 8'h 98;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_OFFSET = 8'h 9c;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET = 8'h a0;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_EXTHT_FAIL_COUNTS_OFFSET = 8'h a4;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_FW_OV_CONTROL_OFFSET = 8'h a8;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_FW_OV_RD_DATA_OFFSET = 8'h ac;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_FW_OV_WR_DATA_OFFSET = 8'h b0;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_FW_OV_FIFO_STS_OFFSET = 8'h b4;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_PRE_COND_FIFO_DEPTH_OFFSET = 8'h b8;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_DEBUG_STATUS_OFFSET = 8'h bc;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_SEED_OFFSET = 8'h c0;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ERR_CODE_OFFSET = 8'h c4;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ERR_CODE_TEST_OFFSET = 8'h c8;
// Reset values for hwext registers and their fields
parameter logic [2:0] ENTROPY_SRC_INTR_TEST_RESVAL = 3'h 0;
@@ -681,6 +727,9 @@
parameter logic [31:0] ENTROPY_SRC_REPCNT_THRESHOLDS_RESVAL = 32'h ffffffff;
parameter logic [15:0] ENTROPY_SRC_REPCNT_THRESHOLDS_FIPS_THRESH_RESVAL = 16'h ffff;
parameter logic [15:0] ENTROPY_SRC_REPCNT_THRESHOLDS_BYPASS_THRESH_RESVAL = 16'h ffff;
+ parameter logic [31:0] ENTROPY_SRC_REPCNTS_THRESHOLDS_RESVAL = 32'h ffffffff;
+ parameter logic [15:0] ENTROPY_SRC_REPCNTS_THRESHOLDS_FIPS_THRESH_RESVAL = 16'h ffff;
+ parameter logic [15:0] ENTROPY_SRC_REPCNTS_THRESHOLDS_BYPASS_THRESH_RESVAL = 16'h ffff;
parameter logic [31:0] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_RESVAL = 32'h ffffffff;
parameter logic [15:0] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_FIPS_THRESH_RESVAL = 16'h ffff;
parameter logic [15:0] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_BYPASS_THRESH_RESVAL = 16'h ffff;
@@ -703,6 +752,7 @@
parameter logic [15:0] ENTROPY_SRC_EXTHT_LO_THRESHOLDS_FIPS_THRESH_RESVAL = 16'h 0;
parameter logic [15:0] ENTROPY_SRC_EXTHT_LO_THRESHOLDS_BYPASS_THRESH_RESVAL = 16'h 0;
parameter logic [31:0] ENTROPY_SRC_REPCNT_HI_WATERMARKS_RESVAL = 32'h 0;
+ parameter logic [31:0] ENTROPY_SRC_REPCNTS_HI_WATERMARKS_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_ADAPTP_HI_WATERMARKS_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_ADAPTP_LO_WATERMARKS_RESVAL = 32'h ffffffff;
parameter logic [15:0] ENTROPY_SRC_ADAPTP_LO_WATERMARKS_FIPS_WATERMARK_RESVAL = 16'h ffff;
@@ -717,6 +767,7 @@
parameter logic [15:0] ENTROPY_SRC_MARKOV_LO_WATERMARKS_FIPS_WATERMARK_RESVAL = 16'h ffff;
parameter logic [15:0] ENTROPY_SRC_MARKOV_LO_WATERMARKS_BYPASS_WATERMARK_RESVAL = 16'h ffff;
parameter logic [31:0] ENTROPY_SRC_REPCNT_TOTAL_FAILS_RESVAL = 32'h 0;
+ parameter logic [31:0] ENTROPY_SRC_REPCNTS_TOTAL_FAILS_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_BUCKET_TOTAL_FAILS_RESVAL = 32'h 0;
@@ -725,7 +776,7 @@
parameter logic [31:0] ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_RESVAL = 32'h 0;
- parameter logic [27:0] ENTROPY_SRC_ALERT_FAIL_COUNTS_RESVAL = 28'h 0;
+ parameter logic [31:0] ENTROPY_SRC_ALERT_FAIL_COUNTS_RESVAL = 32'h 0;
parameter logic [7:0] ENTROPY_SRC_EXTHT_FAIL_COUNTS_RESVAL = 8'h 0;
parameter logic [31:0] ENTROPY_SRC_FW_OV_RD_DATA_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_FW_OV_WR_DATA_RESVAL = 32'h 0;
@@ -746,6 +797,7 @@
ENTROPY_SRC_ENTROPY_DATA,
ENTROPY_SRC_HEALTH_TEST_WINDOWS,
ENTROPY_SRC_REPCNT_THRESHOLDS,
+ ENTROPY_SRC_REPCNTS_THRESHOLDS,
ENTROPY_SRC_ADAPTP_HI_THRESHOLDS,
ENTROPY_SRC_ADAPTP_LO_THRESHOLDS,
ENTROPY_SRC_BUCKET_THRESHOLDS,
@@ -754,6 +806,7 @@
ENTROPY_SRC_EXTHT_HI_THRESHOLDS,
ENTROPY_SRC_EXTHT_LO_THRESHOLDS,
ENTROPY_SRC_REPCNT_HI_WATERMARKS,
+ ENTROPY_SRC_REPCNTS_HI_WATERMARKS,
ENTROPY_SRC_ADAPTP_HI_WATERMARKS,
ENTROPY_SRC_ADAPTP_LO_WATERMARKS,
ENTROPY_SRC_EXTHT_HI_WATERMARKS,
@@ -762,6 +815,7 @@
ENTROPY_SRC_MARKOV_HI_WATERMARKS,
ENTROPY_SRC_MARKOV_LO_WATERMARKS,
ENTROPY_SRC_REPCNT_TOTAL_FAILS,
+ ENTROPY_SRC_REPCNTS_TOTAL_FAILS,
ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS,
ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS,
ENTROPY_SRC_BUCKET_TOTAL_FAILS,
@@ -785,7 +839,7 @@
} entropy_src_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] ENTROPY_SRC_PERMIT [48] = '{
+ parameter logic [3:0] ENTROPY_SRC_PERMIT [51] = '{
4'b 0001, // index[ 0] ENTROPY_SRC_INTR_STATE
4'b 0001, // index[ 1] ENTROPY_SRC_INTR_ENABLE
4'b 0001, // index[ 2] ENTROPY_SRC_INTR_TEST
@@ -798,42 +852,45 @@
4'b 1111, // index[ 9] ENTROPY_SRC_ENTROPY_DATA
4'b 1111, // index[10] ENTROPY_SRC_HEALTH_TEST_WINDOWS
4'b 1111, // index[11] ENTROPY_SRC_REPCNT_THRESHOLDS
- 4'b 1111, // index[12] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS
- 4'b 1111, // index[13] ENTROPY_SRC_ADAPTP_LO_THRESHOLDS
- 4'b 1111, // index[14] ENTROPY_SRC_BUCKET_THRESHOLDS
- 4'b 1111, // index[15] ENTROPY_SRC_MARKOV_HI_THRESHOLDS
- 4'b 1111, // index[16] ENTROPY_SRC_MARKOV_LO_THRESHOLDS
- 4'b 1111, // index[17] ENTROPY_SRC_EXTHT_HI_THRESHOLDS
- 4'b 1111, // index[18] ENTROPY_SRC_EXTHT_LO_THRESHOLDS
- 4'b 1111, // index[19] ENTROPY_SRC_REPCNT_HI_WATERMARKS
- 4'b 1111, // index[20] ENTROPY_SRC_ADAPTP_HI_WATERMARKS
- 4'b 1111, // index[21] ENTROPY_SRC_ADAPTP_LO_WATERMARKS
- 4'b 1111, // index[22] ENTROPY_SRC_EXTHT_HI_WATERMARKS
- 4'b 1111, // index[23] ENTROPY_SRC_EXTHT_LO_WATERMARKS
- 4'b 1111, // index[24] ENTROPY_SRC_BUCKET_HI_WATERMARKS
- 4'b 1111, // index[25] ENTROPY_SRC_MARKOV_HI_WATERMARKS
- 4'b 1111, // index[26] ENTROPY_SRC_MARKOV_LO_WATERMARKS
- 4'b 1111, // index[27] ENTROPY_SRC_REPCNT_TOTAL_FAILS
- 4'b 1111, // index[28] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS
- 4'b 1111, // index[29] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS
- 4'b 1111, // index[30] ENTROPY_SRC_BUCKET_TOTAL_FAILS
- 4'b 1111, // index[31] ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS
- 4'b 1111, // index[32] ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS
- 4'b 1111, // index[33] ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS
- 4'b 1111, // index[34] ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS
- 4'b 1111, // index[35] ENTROPY_SRC_ALERT_THRESHOLD
- 4'b 1111, // index[36] ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS
- 4'b 1111, // index[37] ENTROPY_SRC_ALERT_FAIL_COUNTS
- 4'b 0001, // index[38] ENTROPY_SRC_EXTHT_FAIL_COUNTS
- 4'b 0001, // index[39] ENTROPY_SRC_FW_OV_CONTROL
- 4'b 1111, // index[40] ENTROPY_SRC_FW_OV_RD_DATA
- 4'b 1111, // index[41] ENTROPY_SRC_FW_OV_WR_DATA
- 4'b 0001, // index[42] ENTROPY_SRC_FW_OV_FIFO_STS
- 4'b 0001, // index[43] ENTROPY_SRC_PRE_COND_FIFO_DEPTH
- 4'b 1111, // index[44] ENTROPY_SRC_DEBUG_STATUS
- 4'b 0001, // index[45] ENTROPY_SRC_SEED
- 4'b 1111, // index[46] ENTROPY_SRC_ERR_CODE
- 4'b 0001 // index[47] ENTROPY_SRC_ERR_CODE_TEST
+ 4'b 1111, // index[12] ENTROPY_SRC_REPCNTS_THRESHOLDS
+ 4'b 1111, // index[13] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS
+ 4'b 1111, // index[14] ENTROPY_SRC_ADAPTP_LO_THRESHOLDS
+ 4'b 1111, // index[15] ENTROPY_SRC_BUCKET_THRESHOLDS
+ 4'b 1111, // index[16] ENTROPY_SRC_MARKOV_HI_THRESHOLDS
+ 4'b 1111, // index[17] ENTROPY_SRC_MARKOV_LO_THRESHOLDS
+ 4'b 1111, // index[18] ENTROPY_SRC_EXTHT_HI_THRESHOLDS
+ 4'b 1111, // index[19] ENTROPY_SRC_EXTHT_LO_THRESHOLDS
+ 4'b 1111, // index[20] ENTROPY_SRC_REPCNT_HI_WATERMARKS
+ 4'b 1111, // index[21] ENTROPY_SRC_REPCNTS_HI_WATERMARKS
+ 4'b 1111, // index[22] ENTROPY_SRC_ADAPTP_HI_WATERMARKS
+ 4'b 1111, // index[23] ENTROPY_SRC_ADAPTP_LO_WATERMARKS
+ 4'b 1111, // index[24] ENTROPY_SRC_EXTHT_HI_WATERMARKS
+ 4'b 1111, // index[25] ENTROPY_SRC_EXTHT_LO_WATERMARKS
+ 4'b 1111, // index[26] ENTROPY_SRC_BUCKET_HI_WATERMARKS
+ 4'b 1111, // index[27] ENTROPY_SRC_MARKOV_HI_WATERMARKS
+ 4'b 1111, // index[28] ENTROPY_SRC_MARKOV_LO_WATERMARKS
+ 4'b 1111, // index[29] ENTROPY_SRC_REPCNT_TOTAL_FAILS
+ 4'b 1111, // index[30] ENTROPY_SRC_REPCNTS_TOTAL_FAILS
+ 4'b 1111, // index[31] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS
+ 4'b 1111, // index[32] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS
+ 4'b 1111, // index[33] ENTROPY_SRC_BUCKET_TOTAL_FAILS
+ 4'b 1111, // index[34] ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS
+ 4'b 1111, // index[35] ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS
+ 4'b 1111, // index[36] ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS
+ 4'b 1111, // index[37] ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS
+ 4'b 1111, // index[38] ENTROPY_SRC_ALERT_THRESHOLD
+ 4'b 1111, // index[39] ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS
+ 4'b 1111, // index[40] ENTROPY_SRC_ALERT_FAIL_COUNTS
+ 4'b 0001, // index[41] ENTROPY_SRC_EXTHT_FAIL_COUNTS
+ 4'b 0001, // index[42] ENTROPY_SRC_FW_OV_CONTROL
+ 4'b 1111, // index[43] ENTROPY_SRC_FW_OV_RD_DATA
+ 4'b 1111, // index[44] ENTROPY_SRC_FW_OV_WR_DATA
+ 4'b 0001, // index[45] ENTROPY_SRC_FW_OV_FIFO_STS
+ 4'b 0001, // index[46] ENTROPY_SRC_PRE_COND_FIFO_DEPTH
+ 4'b 1111, // index[47] ENTROPY_SRC_DEBUG_STATUS
+ 4'b 0001, // index[48] ENTROPY_SRC_SEED
+ 4'b 1111, // index[49] ENTROPY_SRC_ERR_CODE
+ 4'b 0001 // index[50] ENTROPY_SRC_ERR_CODE_TEST
};
endpackage
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
index 01a456b..9e13321 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
@@ -168,6 +168,9 @@
logic conf_extht_enable_qs;
logic conf_extht_enable_wd;
logic conf_extht_enable_we;
+ logic conf_repcnts_disable_qs;
+ logic conf_repcnts_disable_wd;
+ logic conf_repcnts_disable_we;
logic [15:0] rate_qs;
logic [15:0] rate_wd;
logic rate_we;
@@ -193,6 +196,14 @@
logic [15:0] repcnt_thresholds_bypass_thresh_wd;
logic repcnt_thresholds_bypass_thresh_we;
logic repcnt_thresholds_bypass_thresh_re;
+ logic [15:0] repcnts_thresholds_fips_thresh_qs;
+ logic [15:0] repcnts_thresholds_fips_thresh_wd;
+ logic repcnts_thresholds_fips_thresh_we;
+ logic repcnts_thresholds_fips_thresh_re;
+ logic [15:0] repcnts_thresholds_bypass_thresh_qs;
+ logic [15:0] repcnts_thresholds_bypass_thresh_wd;
+ logic repcnts_thresholds_bypass_thresh_we;
+ logic repcnts_thresholds_bypass_thresh_re;
logic [15:0] adaptp_hi_thresholds_fips_thresh_qs;
logic [15:0] adaptp_hi_thresholds_fips_thresh_wd;
logic adaptp_hi_thresholds_fips_thresh_we;
@@ -253,6 +264,10 @@
logic repcnt_hi_watermarks_fips_watermark_re;
logic [15:0] repcnt_hi_watermarks_bypass_watermark_qs;
logic repcnt_hi_watermarks_bypass_watermark_re;
+ logic [15:0] repcnts_hi_watermarks_fips_watermark_qs;
+ logic repcnts_hi_watermarks_fips_watermark_re;
+ logic [15:0] repcnts_hi_watermarks_bypass_watermark_qs;
+ logic repcnts_hi_watermarks_bypass_watermark_re;
logic [15:0] adaptp_hi_watermarks_fips_watermark_qs;
logic adaptp_hi_watermarks_fips_watermark_re;
logic [15:0] adaptp_hi_watermarks_bypass_watermark_qs;
@@ -283,6 +298,8 @@
logic markov_lo_watermarks_bypass_watermark_re;
logic [31:0] repcnt_total_fails_qs;
logic repcnt_total_fails_re;
+ logic [31:0] repcnts_total_fails_qs;
+ logic repcnts_total_fails_re;
logic [31:0] adaptp_hi_total_fails_qs;
logic adaptp_hi_total_fails_re;
logic [31:0] adaptp_lo_total_fails_qs;
@@ -314,6 +331,8 @@
logic alert_fail_counts_markov_hi_fail_count_re;
logic [3:0] alert_fail_counts_markov_lo_fail_count_qs;
logic alert_fail_counts_markov_lo_fail_count_re;
+ logic [3:0] alert_fail_counts_repcnts_fail_count_qs;
+ logic alert_fail_counts_repcnts_fail_count_re;
logic [3:0] extht_fail_counts_extht_hi_fail_count_qs;
logic extht_fail_counts_extht_hi_fail_count_re;
logic [3:0] extht_fail_counts_extht_lo_fail_count_qs;
@@ -911,6 +930,32 @@
);
+ // F[repcnts_disable]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_conf_repcnts_disable (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (conf_repcnts_disable_we & regwen_qs),
+ .wd (conf_repcnts_disable_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.conf.repcnts_disable.q ),
+
+ // to register interface (read)
+ .qs (conf_repcnts_disable_qs)
+ );
+
+
// R[rate]: V(False)
prim_subreg #(
@@ -1096,6 +1141,40 @@
);
+ // R[repcnts_thresholds]: V(True)
+
+ // F[fips_thresh]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_repcnts_thresholds_fips_thresh (
+ .re (repcnts_thresholds_fips_thresh_re),
+ // qualified with register enable
+ .we (repcnts_thresholds_fips_thresh_we & regwen_qs),
+ .wd (repcnts_thresholds_fips_thresh_wd),
+ .d (hw2reg.repcnts_thresholds.fips_thresh.d),
+ .qre (),
+ .qe (reg2hw.repcnts_thresholds.fips_thresh.qe),
+ .q (reg2hw.repcnts_thresholds.fips_thresh.q ),
+ .qs (repcnts_thresholds_fips_thresh_qs)
+ );
+
+
+ // F[bypass_thresh]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_repcnts_thresholds_bypass_thresh (
+ .re (repcnts_thresholds_bypass_thresh_re),
+ // qualified with register enable
+ .we (repcnts_thresholds_bypass_thresh_we & regwen_qs),
+ .wd (repcnts_thresholds_bypass_thresh_wd),
+ .d (hw2reg.repcnts_thresholds.bypass_thresh.d),
+ .qre (),
+ .qe (reg2hw.repcnts_thresholds.bypass_thresh.qe),
+ .q (reg2hw.repcnts_thresholds.bypass_thresh.q ),
+ .qs (repcnts_thresholds_bypass_thresh_qs)
+ );
+
+
// R[adaptp_hi_thresholds]: V(True)
// F[fips_thresh]: 15:0
@@ -1366,6 +1445,38 @@
);
+ // R[repcnts_hi_watermarks]: V(True)
+
+ // F[fips_watermark]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_repcnts_hi_watermarks_fips_watermark (
+ .re (repcnts_hi_watermarks_fips_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.repcnts_hi_watermarks.fips_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (repcnts_hi_watermarks_fips_watermark_qs)
+ );
+
+
+ // F[bypass_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_repcnts_hi_watermarks_bypass_watermark (
+ .re (repcnts_hi_watermarks_bypass_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.repcnts_hi_watermarks.bypass_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (repcnts_hi_watermarks_bypass_watermark_qs)
+ );
+
+
// R[adaptp_hi_watermarks]: V(True)
// F[fips_watermark]: 15:0
@@ -1606,6 +1717,22 @@
);
+ // R[repcnts_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_repcnts_total_fails (
+ .re (repcnts_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.repcnts_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (repcnts_total_fails_qs)
+ );
+
+
// R[adaptp_hi_total_fails]: V(True)
prim_subreg_ext #(
@@ -1853,6 +1980,21 @@
);
+ // F[repcnts_fail_count]: 31:28
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_repcnts_fail_count (
+ .re (alert_fail_counts_repcnts_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.repcnts_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_repcnts_fail_count_qs)
+ );
+
+
// R[extht_fail_counts]: V(True)
// F[extht_hi_fail_count]: 3:0
@@ -2405,7 +2547,7 @@
- logic [47:0] addr_hit;
+ logic [50:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ENTROPY_SRC_INTR_STATE_OFFSET);
@@ -2420,42 +2562,45 @@
addr_hit[ 9] = (reg_addr == ENTROPY_SRC_ENTROPY_DATA_OFFSET);
addr_hit[10] = (reg_addr == ENTROPY_SRC_HEALTH_TEST_WINDOWS_OFFSET);
addr_hit[11] = (reg_addr == ENTROPY_SRC_REPCNT_THRESHOLDS_OFFSET);
- addr_hit[12] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET);
- addr_hit[13] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET);
- addr_hit[14] = (reg_addr == ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET);
- addr_hit[15] = (reg_addr == ENTROPY_SRC_MARKOV_HI_THRESHOLDS_OFFSET);
- addr_hit[16] = (reg_addr == ENTROPY_SRC_MARKOV_LO_THRESHOLDS_OFFSET);
- addr_hit[17] = (reg_addr == ENTROPY_SRC_EXTHT_HI_THRESHOLDS_OFFSET);
- addr_hit[18] = (reg_addr == ENTROPY_SRC_EXTHT_LO_THRESHOLDS_OFFSET);
- addr_hit[19] = (reg_addr == ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET);
- addr_hit[20] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET);
- addr_hit[21] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET);
- addr_hit[22] = (reg_addr == ENTROPY_SRC_EXTHT_HI_WATERMARKS_OFFSET);
- addr_hit[23] = (reg_addr == ENTROPY_SRC_EXTHT_LO_WATERMARKS_OFFSET);
- addr_hit[24] = (reg_addr == ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET);
- addr_hit[25] = (reg_addr == ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET);
- addr_hit[26] = (reg_addr == ENTROPY_SRC_MARKOV_LO_WATERMARKS_OFFSET);
- addr_hit[27] = (reg_addr == ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET);
- addr_hit[28] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET);
- addr_hit[29] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET);
- addr_hit[30] = (reg_addr == ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET);
- addr_hit[31] = (reg_addr == ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_OFFSET);
- addr_hit[32] = (reg_addr == ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_OFFSET);
- addr_hit[33] = (reg_addr == ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_OFFSET);
- addr_hit[34] = (reg_addr == ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_OFFSET);
- addr_hit[35] = (reg_addr == ENTROPY_SRC_ALERT_THRESHOLD_OFFSET);
- addr_hit[36] = (reg_addr == ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_OFFSET);
- addr_hit[37] = (reg_addr == ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET);
- addr_hit[38] = (reg_addr == ENTROPY_SRC_EXTHT_FAIL_COUNTS_OFFSET);
- addr_hit[39] = (reg_addr == ENTROPY_SRC_FW_OV_CONTROL_OFFSET);
- addr_hit[40] = (reg_addr == ENTROPY_SRC_FW_OV_RD_DATA_OFFSET);
- addr_hit[41] = (reg_addr == ENTROPY_SRC_FW_OV_WR_DATA_OFFSET);
- addr_hit[42] = (reg_addr == ENTROPY_SRC_FW_OV_FIFO_STS_OFFSET);
- addr_hit[43] = (reg_addr == ENTROPY_SRC_PRE_COND_FIFO_DEPTH_OFFSET);
- addr_hit[44] = (reg_addr == ENTROPY_SRC_DEBUG_STATUS_OFFSET);
- addr_hit[45] = (reg_addr == ENTROPY_SRC_SEED_OFFSET);
- addr_hit[46] = (reg_addr == ENTROPY_SRC_ERR_CODE_OFFSET);
- addr_hit[47] = (reg_addr == ENTROPY_SRC_ERR_CODE_TEST_OFFSET);
+ addr_hit[12] = (reg_addr == ENTROPY_SRC_REPCNTS_THRESHOLDS_OFFSET);
+ addr_hit[13] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET);
+ addr_hit[14] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET);
+ addr_hit[15] = (reg_addr == ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET);
+ addr_hit[16] = (reg_addr == ENTROPY_SRC_MARKOV_HI_THRESHOLDS_OFFSET);
+ addr_hit[17] = (reg_addr == ENTROPY_SRC_MARKOV_LO_THRESHOLDS_OFFSET);
+ addr_hit[18] = (reg_addr == ENTROPY_SRC_EXTHT_HI_THRESHOLDS_OFFSET);
+ addr_hit[19] = (reg_addr == ENTROPY_SRC_EXTHT_LO_THRESHOLDS_OFFSET);
+ addr_hit[20] = (reg_addr == ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET);
+ addr_hit[21] = (reg_addr == ENTROPY_SRC_REPCNTS_HI_WATERMARKS_OFFSET);
+ addr_hit[22] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET);
+ addr_hit[23] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET);
+ addr_hit[24] = (reg_addr == ENTROPY_SRC_EXTHT_HI_WATERMARKS_OFFSET);
+ addr_hit[25] = (reg_addr == ENTROPY_SRC_EXTHT_LO_WATERMARKS_OFFSET);
+ addr_hit[26] = (reg_addr == ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET);
+ addr_hit[27] = (reg_addr == ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET);
+ addr_hit[28] = (reg_addr == ENTROPY_SRC_MARKOV_LO_WATERMARKS_OFFSET);
+ addr_hit[29] = (reg_addr == ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET);
+ addr_hit[30] = (reg_addr == ENTROPY_SRC_REPCNTS_TOTAL_FAILS_OFFSET);
+ addr_hit[31] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET);
+ addr_hit[32] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET);
+ addr_hit[33] = (reg_addr == ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET);
+ addr_hit[34] = (reg_addr == ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_OFFSET);
+ addr_hit[35] = (reg_addr == ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_OFFSET);
+ addr_hit[36] = (reg_addr == ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_OFFSET);
+ addr_hit[37] = (reg_addr == ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_OFFSET);
+ addr_hit[38] = (reg_addr == ENTROPY_SRC_ALERT_THRESHOLD_OFFSET);
+ addr_hit[39] = (reg_addr == ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_OFFSET);
+ addr_hit[40] = (reg_addr == ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET);
+ addr_hit[41] = (reg_addr == ENTROPY_SRC_EXTHT_FAIL_COUNTS_OFFSET);
+ addr_hit[42] = (reg_addr == ENTROPY_SRC_FW_OV_CONTROL_OFFSET);
+ addr_hit[43] = (reg_addr == ENTROPY_SRC_FW_OV_RD_DATA_OFFSET);
+ addr_hit[44] = (reg_addr == ENTROPY_SRC_FW_OV_WR_DATA_OFFSET);
+ addr_hit[45] = (reg_addr == ENTROPY_SRC_FW_OV_FIFO_STS_OFFSET);
+ addr_hit[46] = (reg_addr == ENTROPY_SRC_PRE_COND_FIFO_DEPTH_OFFSET);
+ addr_hit[47] = (reg_addr == ENTROPY_SRC_DEBUG_STATUS_OFFSET);
+ addr_hit[48] = (reg_addr == ENTROPY_SRC_SEED_OFFSET);
+ addr_hit[49] = (reg_addr == ENTROPY_SRC_ERR_CODE_OFFSET);
+ addr_hit[50] = (reg_addr == ENTROPY_SRC_ERR_CODE_TEST_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -2511,6 +2656,9 @@
if (addr_hit[45] && reg_we && (ENTROPY_SRC_PERMIT[45] != (ENTROPY_SRC_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[46] && reg_we && (ENTROPY_SRC_PERMIT[46] != (ENTROPY_SRC_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[47] && reg_we && (ENTROPY_SRC_PERMIT[47] != (ENTROPY_SRC_PERMIT[47] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[48] && reg_we && (ENTROPY_SRC_PERMIT[48] != (ENTROPY_SRC_PERMIT[48] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[49] && reg_we && (ENTROPY_SRC_PERMIT[49] != (ENTROPY_SRC_PERMIT[49] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[50] && reg_we && (ENTROPY_SRC_PERMIT[50] != (ENTROPY_SRC_PERMIT[50] & reg_be))) wr_err = 1'b1 ;
end
assign intr_state_es_entropy_valid_we = addr_hit[0] & reg_we & !reg_error;
@@ -2579,6 +2727,9 @@
assign conf_extht_enable_we = addr_hit[6] & reg_we & !reg_error;
assign conf_extht_enable_wd = reg_wdata[12];
+ assign conf_repcnts_disable_we = addr_hit[6] & reg_we & !reg_error;
+ assign conf_repcnts_disable_wd = reg_wdata[13];
+
assign rate_we = addr_hit[7] & reg_we & !reg_error;
assign rate_wd = reg_wdata[15:0];
@@ -2604,168 +2755,184 @@
assign repcnt_thresholds_bypass_thresh_wd = reg_wdata[31:16];
assign repcnt_thresholds_bypass_thresh_re = addr_hit[11] & reg_re & !reg_error;
- assign adaptp_hi_thresholds_fips_thresh_we = addr_hit[12] & reg_we & !reg_error;
+ assign repcnts_thresholds_fips_thresh_we = addr_hit[12] & reg_we & !reg_error;
+ assign repcnts_thresholds_fips_thresh_wd = reg_wdata[15:0];
+ assign repcnts_thresholds_fips_thresh_re = addr_hit[12] & reg_re & !reg_error;
+
+ assign repcnts_thresholds_bypass_thresh_we = addr_hit[12] & reg_we & !reg_error;
+ assign repcnts_thresholds_bypass_thresh_wd = reg_wdata[31:16];
+ assign repcnts_thresholds_bypass_thresh_re = addr_hit[12] & reg_re & !reg_error;
+
+ assign adaptp_hi_thresholds_fips_thresh_we = addr_hit[13] & reg_we & !reg_error;
assign adaptp_hi_thresholds_fips_thresh_wd = reg_wdata[15:0];
- assign adaptp_hi_thresholds_fips_thresh_re = addr_hit[12] & reg_re & !reg_error;
+ assign adaptp_hi_thresholds_fips_thresh_re = addr_hit[13] & reg_re & !reg_error;
- assign adaptp_hi_thresholds_bypass_thresh_we = addr_hit[12] & reg_we & !reg_error;
+ assign adaptp_hi_thresholds_bypass_thresh_we = addr_hit[13] & reg_we & !reg_error;
assign adaptp_hi_thresholds_bypass_thresh_wd = reg_wdata[31:16];
- assign adaptp_hi_thresholds_bypass_thresh_re = addr_hit[12] & reg_re & !reg_error;
+ assign adaptp_hi_thresholds_bypass_thresh_re = addr_hit[13] & reg_re & !reg_error;
- assign adaptp_lo_thresholds_fips_thresh_we = addr_hit[13] & reg_we & !reg_error;
+ assign adaptp_lo_thresholds_fips_thresh_we = addr_hit[14] & reg_we & !reg_error;
assign adaptp_lo_thresholds_fips_thresh_wd = reg_wdata[15:0];
- assign adaptp_lo_thresholds_fips_thresh_re = addr_hit[13] & reg_re & !reg_error;
+ assign adaptp_lo_thresholds_fips_thresh_re = addr_hit[14] & reg_re & !reg_error;
- assign adaptp_lo_thresholds_bypass_thresh_we = addr_hit[13] & reg_we & !reg_error;
+ assign adaptp_lo_thresholds_bypass_thresh_we = addr_hit[14] & reg_we & !reg_error;
assign adaptp_lo_thresholds_bypass_thresh_wd = reg_wdata[31:16];
- assign adaptp_lo_thresholds_bypass_thresh_re = addr_hit[13] & reg_re & !reg_error;
+ assign adaptp_lo_thresholds_bypass_thresh_re = addr_hit[14] & reg_re & !reg_error;
- assign bucket_thresholds_fips_thresh_we = addr_hit[14] & reg_we & !reg_error;
+ assign bucket_thresholds_fips_thresh_we = addr_hit[15] & reg_we & !reg_error;
assign bucket_thresholds_fips_thresh_wd = reg_wdata[15:0];
- assign bucket_thresholds_fips_thresh_re = addr_hit[14] & reg_re & !reg_error;
+ assign bucket_thresholds_fips_thresh_re = addr_hit[15] & reg_re & !reg_error;
- assign bucket_thresholds_bypass_thresh_we = addr_hit[14] & reg_we & !reg_error;
+ assign bucket_thresholds_bypass_thresh_we = addr_hit[15] & reg_we & !reg_error;
assign bucket_thresholds_bypass_thresh_wd = reg_wdata[31:16];
- assign bucket_thresholds_bypass_thresh_re = addr_hit[14] & reg_re & !reg_error;
+ assign bucket_thresholds_bypass_thresh_re = addr_hit[15] & reg_re & !reg_error;
- assign markov_hi_thresholds_fips_thresh_we = addr_hit[15] & reg_we & !reg_error;
+ assign markov_hi_thresholds_fips_thresh_we = addr_hit[16] & reg_we & !reg_error;
assign markov_hi_thresholds_fips_thresh_wd = reg_wdata[15:0];
- assign markov_hi_thresholds_fips_thresh_re = addr_hit[15] & reg_re & !reg_error;
+ assign markov_hi_thresholds_fips_thresh_re = addr_hit[16] & reg_re & !reg_error;
- assign markov_hi_thresholds_bypass_thresh_we = addr_hit[15] & reg_we & !reg_error;
+ assign markov_hi_thresholds_bypass_thresh_we = addr_hit[16] & reg_we & !reg_error;
assign markov_hi_thresholds_bypass_thresh_wd = reg_wdata[31:16];
- assign markov_hi_thresholds_bypass_thresh_re = addr_hit[15] & reg_re & !reg_error;
+ assign markov_hi_thresholds_bypass_thresh_re = addr_hit[16] & reg_re & !reg_error;
- assign markov_lo_thresholds_fips_thresh_we = addr_hit[16] & reg_we & !reg_error;
+ assign markov_lo_thresholds_fips_thresh_we = addr_hit[17] & reg_we & !reg_error;
assign markov_lo_thresholds_fips_thresh_wd = reg_wdata[15:0];
- assign markov_lo_thresholds_fips_thresh_re = addr_hit[16] & reg_re & !reg_error;
+ assign markov_lo_thresholds_fips_thresh_re = addr_hit[17] & reg_re & !reg_error;
- assign markov_lo_thresholds_bypass_thresh_we = addr_hit[16] & reg_we & !reg_error;
+ assign markov_lo_thresholds_bypass_thresh_we = addr_hit[17] & reg_we & !reg_error;
assign markov_lo_thresholds_bypass_thresh_wd = reg_wdata[31:16];
- assign markov_lo_thresholds_bypass_thresh_re = addr_hit[16] & reg_re & !reg_error;
+ assign markov_lo_thresholds_bypass_thresh_re = addr_hit[17] & reg_re & !reg_error;
- assign extht_hi_thresholds_fips_thresh_we = addr_hit[17] & reg_we & !reg_error;
+ assign extht_hi_thresholds_fips_thresh_we = addr_hit[18] & reg_we & !reg_error;
assign extht_hi_thresholds_fips_thresh_wd = reg_wdata[15:0];
- assign extht_hi_thresholds_fips_thresh_re = addr_hit[17] & reg_re & !reg_error;
+ assign extht_hi_thresholds_fips_thresh_re = addr_hit[18] & reg_re & !reg_error;
- assign extht_hi_thresholds_bypass_thresh_we = addr_hit[17] & reg_we & !reg_error;
+ assign extht_hi_thresholds_bypass_thresh_we = addr_hit[18] & reg_we & !reg_error;
assign extht_hi_thresholds_bypass_thresh_wd = reg_wdata[31:16];
- assign extht_hi_thresholds_bypass_thresh_re = addr_hit[17] & reg_re & !reg_error;
+ assign extht_hi_thresholds_bypass_thresh_re = addr_hit[18] & reg_re & !reg_error;
- assign extht_lo_thresholds_fips_thresh_we = addr_hit[18] & reg_we & !reg_error;
+ assign extht_lo_thresholds_fips_thresh_we = addr_hit[19] & reg_we & !reg_error;
assign extht_lo_thresholds_fips_thresh_wd = reg_wdata[15:0];
- assign extht_lo_thresholds_fips_thresh_re = addr_hit[18] & reg_re & !reg_error;
+ assign extht_lo_thresholds_fips_thresh_re = addr_hit[19] & reg_re & !reg_error;
- assign extht_lo_thresholds_bypass_thresh_we = addr_hit[18] & reg_we & !reg_error;
+ assign extht_lo_thresholds_bypass_thresh_we = addr_hit[19] & reg_we & !reg_error;
assign extht_lo_thresholds_bypass_thresh_wd = reg_wdata[31:16];
- assign extht_lo_thresholds_bypass_thresh_re = addr_hit[18] & reg_re & !reg_error;
+ assign extht_lo_thresholds_bypass_thresh_re = addr_hit[19] & reg_re & !reg_error;
- assign repcnt_hi_watermarks_fips_watermark_re = addr_hit[19] & reg_re & !reg_error;
+ assign repcnt_hi_watermarks_fips_watermark_re = addr_hit[20] & reg_re & !reg_error;
- assign repcnt_hi_watermarks_bypass_watermark_re = addr_hit[19] & reg_re & !reg_error;
+ assign repcnt_hi_watermarks_bypass_watermark_re = addr_hit[20] & reg_re & !reg_error;
- assign adaptp_hi_watermarks_fips_watermark_re = addr_hit[20] & reg_re & !reg_error;
+ assign repcnts_hi_watermarks_fips_watermark_re = addr_hit[21] & reg_re & !reg_error;
- assign adaptp_hi_watermarks_bypass_watermark_re = addr_hit[20] & reg_re & !reg_error;
+ assign repcnts_hi_watermarks_bypass_watermark_re = addr_hit[21] & reg_re & !reg_error;
- assign adaptp_lo_watermarks_fips_watermark_re = addr_hit[21] & reg_re & !reg_error;
+ assign adaptp_hi_watermarks_fips_watermark_re = addr_hit[22] & reg_re & !reg_error;
- assign adaptp_lo_watermarks_bypass_watermark_re = addr_hit[21] & reg_re & !reg_error;
+ assign adaptp_hi_watermarks_bypass_watermark_re = addr_hit[22] & reg_re & !reg_error;
- assign extht_hi_watermarks_fips_watermark_re = addr_hit[22] & reg_re & !reg_error;
+ assign adaptp_lo_watermarks_fips_watermark_re = addr_hit[23] & reg_re & !reg_error;
- assign extht_hi_watermarks_bypass_watermark_re = addr_hit[22] & reg_re & !reg_error;
+ assign adaptp_lo_watermarks_bypass_watermark_re = addr_hit[23] & reg_re & !reg_error;
- assign extht_lo_watermarks_fips_watermark_re = addr_hit[23] & reg_re & !reg_error;
+ assign extht_hi_watermarks_fips_watermark_re = addr_hit[24] & reg_re & !reg_error;
- assign extht_lo_watermarks_bypass_watermark_re = addr_hit[23] & reg_re & !reg_error;
+ assign extht_hi_watermarks_bypass_watermark_re = addr_hit[24] & reg_re & !reg_error;
- assign bucket_hi_watermarks_fips_watermark_re = addr_hit[24] & reg_re & !reg_error;
+ assign extht_lo_watermarks_fips_watermark_re = addr_hit[25] & reg_re & !reg_error;
- assign bucket_hi_watermarks_bypass_watermark_re = addr_hit[24] & reg_re & !reg_error;
+ assign extht_lo_watermarks_bypass_watermark_re = addr_hit[25] & reg_re & !reg_error;
- assign markov_hi_watermarks_fips_watermark_re = addr_hit[25] & reg_re & !reg_error;
+ assign bucket_hi_watermarks_fips_watermark_re = addr_hit[26] & reg_re & !reg_error;
- assign markov_hi_watermarks_bypass_watermark_re = addr_hit[25] & reg_re & !reg_error;
+ assign bucket_hi_watermarks_bypass_watermark_re = addr_hit[26] & reg_re & !reg_error;
- assign markov_lo_watermarks_fips_watermark_re = addr_hit[26] & reg_re & !reg_error;
+ assign markov_hi_watermarks_fips_watermark_re = addr_hit[27] & reg_re & !reg_error;
- assign markov_lo_watermarks_bypass_watermark_re = addr_hit[26] & reg_re & !reg_error;
+ assign markov_hi_watermarks_bypass_watermark_re = addr_hit[27] & reg_re & !reg_error;
- assign repcnt_total_fails_re = addr_hit[27] & reg_re & !reg_error;
+ assign markov_lo_watermarks_fips_watermark_re = addr_hit[28] & reg_re & !reg_error;
- assign adaptp_hi_total_fails_re = addr_hit[28] & reg_re & !reg_error;
+ assign markov_lo_watermarks_bypass_watermark_re = addr_hit[28] & reg_re & !reg_error;
- assign adaptp_lo_total_fails_re = addr_hit[29] & reg_re & !reg_error;
+ assign repcnt_total_fails_re = addr_hit[29] & reg_re & !reg_error;
- assign bucket_total_fails_re = addr_hit[30] & reg_re & !reg_error;
+ assign repcnts_total_fails_re = addr_hit[30] & reg_re & !reg_error;
- assign markov_hi_total_fails_re = addr_hit[31] & reg_re & !reg_error;
+ assign adaptp_hi_total_fails_re = addr_hit[31] & reg_re & !reg_error;
- assign markov_lo_total_fails_re = addr_hit[32] & reg_re & !reg_error;
+ assign adaptp_lo_total_fails_re = addr_hit[32] & reg_re & !reg_error;
- assign extht_hi_total_fails_re = addr_hit[33] & reg_re & !reg_error;
+ assign bucket_total_fails_re = addr_hit[33] & reg_re & !reg_error;
- assign extht_lo_total_fails_re = addr_hit[34] & reg_re & !reg_error;
+ assign markov_hi_total_fails_re = addr_hit[34] & reg_re & !reg_error;
- assign alert_threshold_we = addr_hit[35] & reg_we & !reg_error;
+ assign markov_lo_total_fails_re = addr_hit[35] & reg_re & !reg_error;
+
+ assign extht_hi_total_fails_re = addr_hit[36] & reg_re & !reg_error;
+
+ assign extht_lo_total_fails_re = addr_hit[37] & reg_re & !reg_error;
+
+ assign alert_threshold_we = addr_hit[38] & reg_we & !reg_error;
assign alert_threshold_wd = reg_wdata[31:0];
- assign alert_summary_fail_counts_re = addr_hit[36] & reg_re & !reg_error;
+ assign alert_summary_fail_counts_re = addr_hit[39] & reg_re & !reg_error;
- assign alert_fail_counts_repcnt_fail_count_re = addr_hit[37] & reg_re & !reg_error;
+ assign alert_fail_counts_repcnt_fail_count_re = addr_hit[40] & reg_re & !reg_error;
- assign alert_fail_counts_adaptp_hi_fail_count_re = addr_hit[37] & reg_re & !reg_error;
+ assign alert_fail_counts_adaptp_hi_fail_count_re = addr_hit[40] & reg_re & !reg_error;
- assign alert_fail_counts_adaptp_lo_fail_count_re = addr_hit[37] & reg_re & !reg_error;
+ assign alert_fail_counts_adaptp_lo_fail_count_re = addr_hit[40] & reg_re & !reg_error;
- assign alert_fail_counts_bucket_fail_count_re = addr_hit[37] & reg_re & !reg_error;
+ assign alert_fail_counts_bucket_fail_count_re = addr_hit[40] & reg_re & !reg_error;
- assign alert_fail_counts_markov_hi_fail_count_re = addr_hit[37] & reg_re & !reg_error;
+ assign alert_fail_counts_markov_hi_fail_count_re = addr_hit[40] & reg_re & !reg_error;
- assign alert_fail_counts_markov_lo_fail_count_re = addr_hit[37] & reg_re & !reg_error;
+ assign alert_fail_counts_markov_lo_fail_count_re = addr_hit[40] & reg_re & !reg_error;
- assign extht_fail_counts_extht_hi_fail_count_re = addr_hit[38] & reg_re & !reg_error;
+ assign alert_fail_counts_repcnts_fail_count_re = addr_hit[40] & reg_re & !reg_error;
- assign extht_fail_counts_extht_lo_fail_count_re = addr_hit[38] & reg_re & !reg_error;
+ assign extht_fail_counts_extht_hi_fail_count_re = addr_hit[41] & reg_re & !reg_error;
- assign fw_ov_control_fw_ov_mode_we = addr_hit[39] & reg_we & !reg_error;
+ assign extht_fail_counts_extht_lo_fail_count_re = addr_hit[41] & reg_re & !reg_error;
+
+ assign fw_ov_control_fw_ov_mode_we = addr_hit[42] & reg_we & !reg_error;
assign fw_ov_control_fw_ov_mode_wd = reg_wdata[0];
- assign fw_ov_control_fw_ov_fifo_reg_rd_we = addr_hit[39] & reg_we & !reg_error;
+ assign fw_ov_control_fw_ov_fifo_reg_rd_we = addr_hit[42] & reg_we & !reg_error;
assign fw_ov_control_fw_ov_fifo_reg_rd_wd = reg_wdata[1];
- assign fw_ov_control_fw_ov_fifo_reg_wr_we = addr_hit[39] & reg_we & !reg_error;
+ assign fw_ov_control_fw_ov_fifo_reg_wr_we = addr_hit[42] & reg_we & !reg_error;
assign fw_ov_control_fw_ov_fifo_reg_wr_wd = reg_wdata[2];
- assign fw_ov_rd_data_re = addr_hit[40] & reg_re & !reg_error;
+ assign fw_ov_rd_data_re = addr_hit[43] & reg_re & !reg_error;
- assign fw_ov_wr_data_we = addr_hit[41] & reg_we & !reg_error;
+ assign fw_ov_wr_data_we = addr_hit[44] & reg_we & !reg_error;
assign fw_ov_wr_data_wd = reg_wdata[31:0];
- assign fw_ov_fifo_sts_re = addr_hit[42] & reg_re & !reg_error;
+ assign fw_ov_fifo_sts_re = addr_hit[45] & reg_re & !reg_error;
- assign pre_cond_fifo_depth_we = addr_hit[43] & reg_we & !reg_error;
+ assign pre_cond_fifo_depth_we = addr_hit[46] & reg_we & !reg_error;
assign pre_cond_fifo_depth_wd = reg_wdata[6:0];
- assign debug_status_entropy_fifo_depth_re = addr_hit[44] & reg_re & !reg_error;
+ assign debug_status_entropy_fifo_depth_re = addr_hit[47] & reg_re & !reg_error;
- assign debug_status_sha3_fsm_re = addr_hit[44] & reg_re & !reg_error;
+ assign debug_status_sha3_fsm_re = addr_hit[47] & reg_re & !reg_error;
- assign debug_status_sha3_block_pr_re = addr_hit[44] & reg_re & !reg_error;
+ assign debug_status_sha3_block_pr_re = addr_hit[47] & reg_re & !reg_error;
- assign debug_status_sha3_squeezing_re = addr_hit[44] & reg_re & !reg_error;
+ assign debug_status_sha3_squeezing_re = addr_hit[47] & reg_re & !reg_error;
- assign debug_status_sha3_absorbed_re = addr_hit[44] & reg_re & !reg_error;
+ assign debug_status_sha3_absorbed_re = addr_hit[47] & reg_re & !reg_error;
- assign debug_status_sha3_err_re = addr_hit[44] & reg_re & !reg_error;
+ assign debug_status_sha3_err_re = addr_hit[47] & reg_re & !reg_error;
- assign debug_status_diag_re = addr_hit[44] & reg_re & !reg_error;
+ assign debug_status_diag_re = addr_hit[47] & reg_re & !reg_error;
- assign seed_we = addr_hit[45] & reg_we & !reg_error;
+ assign seed_we = addr_hit[48] & reg_we & !reg_error;
assign seed_wd = reg_wdata[3:0];
- assign err_code_test_we = addr_hit[47] & reg_we & !reg_error;
+ assign err_code_test_we = addr_hit[50] & reg_we & !reg_error;
assign err_code_test_wd = reg_wdata[4:0];
// Read data return
@@ -2816,6 +2983,7 @@
reg_rdata_next[9] = conf_rng_bit_en_qs;
reg_rdata_next[11:10] = conf_rng_bit_sel_qs;
reg_rdata_next[12] = conf_extht_enable_qs;
+ reg_rdata_next[13] = conf_repcnts_disable_qs;
end
addr_hit[7]: begin
@@ -2842,157 +3010,172 @@
end
addr_hit[12]: begin
+ reg_rdata_next[15:0] = repcnts_thresholds_fips_thresh_qs;
+ reg_rdata_next[31:16] = repcnts_thresholds_bypass_thresh_qs;
+ end
+
+ addr_hit[13]: begin
reg_rdata_next[15:0] = adaptp_hi_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = adaptp_hi_thresholds_bypass_thresh_qs;
end
- addr_hit[13]: begin
+ addr_hit[14]: begin
reg_rdata_next[15:0] = adaptp_lo_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = adaptp_lo_thresholds_bypass_thresh_qs;
end
- addr_hit[14]: begin
+ addr_hit[15]: begin
reg_rdata_next[15:0] = bucket_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = bucket_thresholds_bypass_thresh_qs;
end
- addr_hit[15]: begin
+ addr_hit[16]: begin
reg_rdata_next[15:0] = markov_hi_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = markov_hi_thresholds_bypass_thresh_qs;
end
- addr_hit[16]: begin
+ addr_hit[17]: begin
reg_rdata_next[15:0] = markov_lo_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = markov_lo_thresholds_bypass_thresh_qs;
end
- addr_hit[17]: begin
+ addr_hit[18]: begin
reg_rdata_next[15:0] = extht_hi_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = extht_hi_thresholds_bypass_thresh_qs;
end
- addr_hit[18]: begin
+ addr_hit[19]: begin
reg_rdata_next[15:0] = extht_lo_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = extht_lo_thresholds_bypass_thresh_qs;
end
- addr_hit[19]: begin
+ addr_hit[20]: begin
reg_rdata_next[15:0] = repcnt_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = repcnt_hi_watermarks_bypass_watermark_qs;
end
- addr_hit[20]: begin
+ addr_hit[21]: begin
+ reg_rdata_next[15:0] = repcnts_hi_watermarks_fips_watermark_qs;
+ reg_rdata_next[31:16] = repcnts_hi_watermarks_bypass_watermark_qs;
+ end
+
+ addr_hit[22]: begin
reg_rdata_next[15:0] = adaptp_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = adaptp_hi_watermarks_bypass_watermark_qs;
end
- addr_hit[21]: begin
+ addr_hit[23]: begin
reg_rdata_next[15:0] = adaptp_lo_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = adaptp_lo_watermarks_bypass_watermark_qs;
end
- addr_hit[22]: begin
+ addr_hit[24]: begin
reg_rdata_next[15:0] = extht_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = extht_hi_watermarks_bypass_watermark_qs;
end
- addr_hit[23]: begin
+ addr_hit[25]: begin
reg_rdata_next[15:0] = extht_lo_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = extht_lo_watermarks_bypass_watermark_qs;
end
- addr_hit[24]: begin
+ addr_hit[26]: begin
reg_rdata_next[15:0] = bucket_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = bucket_hi_watermarks_bypass_watermark_qs;
end
- addr_hit[25]: begin
+ addr_hit[27]: begin
reg_rdata_next[15:0] = markov_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = markov_hi_watermarks_bypass_watermark_qs;
end
- addr_hit[26]: begin
+ addr_hit[28]: begin
reg_rdata_next[15:0] = markov_lo_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = markov_lo_watermarks_bypass_watermark_qs;
end
- addr_hit[27]: begin
+ addr_hit[29]: begin
reg_rdata_next[31:0] = repcnt_total_fails_qs;
end
- addr_hit[28]: begin
- reg_rdata_next[31:0] = adaptp_hi_total_fails_qs;
- end
-
- addr_hit[29]: begin
- reg_rdata_next[31:0] = adaptp_lo_total_fails_qs;
- end
-
addr_hit[30]: begin
- reg_rdata_next[31:0] = bucket_total_fails_qs;
+ reg_rdata_next[31:0] = repcnts_total_fails_qs;
end
addr_hit[31]: begin
- reg_rdata_next[31:0] = markov_hi_total_fails_qs;
+ reg_rdata_next[31:0] = adaptp_hi_total_fails_qs;
end
addr_hit[32]: begin
- reg_rdata_next[31:0] = markov_lo_total_fails_qs;
+ reg_rdata_next[31:0] = adaptp_lo_total_fails_qs;
end
addr_hit[33]: begin
- reg_rdata_next[31:0] = extht_hi_total_fails_qs;
+ reg_rdata_next[31:0] = bucket_total_fails_qs;
end
addr_hit[34]: begin
- reg_rdata_next[31:0] = extht_lo_total_fails_qs;
+ reg_rdata_next[31:0] = markov_hi_total_fails_qs;
end
addr_hit[35]: begin
- reg_rdata_next[31:0] = alert_threshold_qs;
+ reg_rdata_next[31:0] = markov_lo_total_fails_qs;
end
addr_hit[36]: begin
- reg_rdata_next[31:0] = alert_summary_fail_counts_qs;
+ reg_rdata_next[31:0] = extht_hi_total_fails_qs;
end
addr_hit[37]: begin
+ reg_rdata_next[31:0] = extht_lo_total_fails_qs;
+ end
+
+ addr_hit[38]: begin
+ reg_rdata_next[31:0] = alert_threshold_qs;
+ end
+
+ addr_hit[39]: begin
+ reg_rdata_next[31:0] = alert_summary_fail_counts_qs;
+ end
+
+ addr_hit[40]: begin
reg_rdata_next[7:4] = alert_fail_counts_repcnt_fail_count_qs;
reg_rdata_next[11:8] = alert_fail_counts_adaptp_hi_fail_count_qs;
reg_rdata_next[15:12] = alert_fail_counts_adaptp_lo_fail_count_qs;
reg_rdata_next[19:16] = alert_fail_counts_bucket_fail_count_qs;
reg_rdata_next[23:20] = alert_fail_counts_markov_hi_fail_count_qs;
reg_rdata_next[27:24] = alert_fail_counts_markov_lo_fail_count_qs;
+ reg_rdata_next[31:28] = alert_fail_counts_repcnts_fail_count_qs;
end
- addr_hit[38]: begin
+ addr_hit[41]: begin
reg_rdata_next[3:0] = extht_fail_counts_extht_hi_fail_count_qs;
reg_rdata_next[7:4] = extht_fail_counts_extht_lo_fail_count_qs;
end
- addr_hit[39]: begin
+ addr_hit[42]: begin
reg_rdata_next[0] = fw_ov_control_fw_ov_mode_qs;
reg_rdata_next[1] = fw_ov_control_fw_ov_fifo_reg_rd_qs;
reg_rdata_next[2] = fw_ov_control_fw_ov_fifo_reg_wr_qs;
end
- addr_hit[40]: begin
+ addr_hit[43]: begin
reg_rdata_next[31:0] = fw_ov_rd_data_qs;
end
- addr_hit[41]: begin
+ addr_hit[44]: begin
reg_rdata_next[31:0] = '0;
end
- addr_hit[42]: begin
+ addr_hit[45]: begin
reg_rdata_next[6:0] = fw_ov_fifo_sts_qs;
end
- addr_hit[43]: begin
+ addr_hit[46]: begin
reg_rdata_next[6:0] = pre_cond_fifo_depth_qs;
end
- addr_hit[44]: begin
+ addr_hit[47]: begin
reg_rdata_next[2:0] = debug_status_entropy_fifo_depth_qs;
reg_rdata_next[5:3] = debug_status_sha3_fsm_qs;
reg_rdata_next[6] = debug_status_sha3_block_pr_qs;
@@ -3002,11 +3185,11 @@
reg_rdata_next[31] = debug_status_diag_qs;
end
- addr_hit[45]: begin
+ addr_hit[48]: begin
reg_rdata_next[3:0] = seed_qs;
end
- addr_hit[46]: begin
+ addr_hit[49]: begin
reg_rdata_next[0] = err_code_sfifo_esrng_err_qs;
reg_rdata_next[1] = err_code_sfifo_precon_err_qs;
reg_rdata_next[2] = err_code_sfifo_esfinal_err_qs;
@@ -3017,7 +3200,7 @@
reg_rdata_next[30] = err_code_fifo_state_err_qs;
end
- addr_hit[47]: begin
+ addr_hit[50]: begin
reg_rdata_next[4:0] = err_code_test_qs;
end
diff --git a/hw/ip/entropy_src/rtl/entropy_src_repcnts_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_repcnts_ht.sv
new file mode 100644
index 0000000..5bbfc86
--- /dev/null
+++ b/hw/ip/entropy_src/rtl/entropy_src_repcnts_ht.sv
@@ -0,0 +1,86 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: entropy_src repetitive count symbol based health test module
+//
+
+module entropy_src_repcnts_ht #(
+ parameter int RegWidth = 16,
+ parameter int RngBusWidth = 4
+) (
+ input logic clk_i,
+ input logic rst_ni,
+
+ // ins req interface
+ input logic [RngBusWidth-1:0] entropy_bit_i,
+ input logic entropy_bit_vld_i,
+ input logic clear_i,
+ input logic active_i,
+ input logic [RegWidth-1:0] thresh_i,
+ output logic [RegWidth-1:0] test_cnt_o,
+ output logic test_fail_pulse_o
+);
+
+ // signals
+ logic samples_match_pulse;
+ logic samples_no_match_pulse;
+ logic rep_cnt_fail;
+
+ // flops
+ logic [RngBusWidth-1:0] prev_sample_q, prev_sample_d;
+ logic [RegWidth-1:0] rep_cntr_q, rep_cntr_d;
+ logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
+
+ always_ff @(posedge clk_i or negedge rst_ni)
+ if (!rst_ni) begin
+ prev_sample_q <= '0;
+ rep_cntr_q <= '{default:0};
+ test_cnt_q <= '0;
+ end else begin
+ prev_sample_q <= prev_sample_d;
+ rep_cntr_q <= rep_cntr_d;
+ test_cnt_q <= test_cnt_d;
+ end
+
+
+ // Repetitive Count Test for symbols
+ //
+ // Test operation
+ // This test will look for catastrophic stuck bit failures. The rep_cntr
+ // uses one as the starting value, just as the NIST algorithm does.
+
+
+ // NIST A sample
+ assign prev_sample_d = (!active_i || clear_i) ? '0 :
+ entropy_bit_vld_i ? entropy_bit_i :
+ prev_sample_q;
+
+ assign samples_match_pulse = entropy_bit_vld_i &&
+ (prev_sample_q == entropy_bit_i);
+ assign samples_no_match_pulse = entropy_bit_vld_i &&
+ (prev_sample_q != entropy_bit_i);
+
+ // NIST B counter
+ assign rep_cntr_d =
+ (!active_i || clear_i) ? {{RegWidth-1{1'b0}},1'b1} :
+ samples_match_pulse ? (rep_cntr_q+1) :
+ samples_no_match_pulse ? '0 :
+ rep_cntr_q;
+
+ assign rep_cnt_fail = (rep_cntr_q >= thresh_i);
+
+
+
+ // Test event counter
+ assign test_cnt_d =
+ (!active_i || clear_i) ? '0 :
+ entropy_bit_vld_i && (|rep_cnt_fail) ? (test_cnt_q+1) :
+ test_cnt_q;
+
+ // the pulses will be only one clock in length
+ assign test_fail_pulse_o = active_i && (test_cnt_q > '0);
+ assign test_cnt_o = test_cnt_q;
+
+
+endmodule
