commit 9e858fb8470a89cc718e99ce5fbab30b9f9c91cd
author Greg Chadwick <gac@lowrisc.org> Mon Oct 12 17:39:16 2020 +0100
committer Greg Chadwick <gac@lowrisc.org> Tue Oct 13 11:08:27 2020 +0100
tree e48c974563be0c433954d0bca1c360fdf51f6c6f
parent a640a85d1ae1b6860b5aca9029774aef81942ad5

[otbn] Style fixes in case statements

Tweaks to formatting so clauses in case statements are either entirely
on one line or consistently use begin/end.

Signed-off-by: Greg Chadwick <gac@lowrisc.org>

hw/ip/otbn/rtl/otbn_controller.sv

diff --git a/hw/ip/otbn/rtl/otbn_controller.sv b/hw/ip/otbn/rtl/otbn_controller.sv
index 7461a18..ff37904 100644
--- a/hw/ip/otbn/rtl/otbn_controller.sv
+++ b/hw/ip/otbn/rtl/otbn_controller.sv
@@ -264,26 +264,19 @@
   // Base ALU Operand A MUX
   always_comb begin
     unique case (insn_dec_base_i.op_a_sel)
-      OpASelRegister:
-        alu_base_operation_o.operand_a = rf_base_rd_data_a_i;
-      OpASelZero:
-        alu_base_operation_o.operand_a = '0;
-      OpASelCurrPc:
-        alu_base_operation_o.operand_a = {{(32 - ImemAddrWidth){1'b0}}, insn_addr_i};
-      default:
-        alu_base_operation_o.operand_a = rf_base_rd_data_a_i;
+      OpASelRegister: alu_base_operation_o.operand_a = rf_base_rd_data_a_i;
+      OpASelZero:     alu_base_operation_o.operand_a = '0;
+      OpASelCurrPc:   alu_base_operation_o.operand_a = {{(32 - ImemAddrWidth){1'b0}}, insn_addr_i};
+      default:        alu_base_operation_o.operand_a = rf_base_rd_data_a_i;
     endcase
   end
 
   // Base ALU Operand B MUX
   always_comb begin
     unique case (insn_dec_base_i.op_b_sel)
-      OpBSelRegister:
-        alu_base_operation_o.operand_b = rf_base_rd_data_b_i;
-      OpBSelImmediate:
-        alu_base_operation_o.operand_b = insn_dec_base_i.i;
-      default:
-        alu_base_operation_o.operand_b = rf_base_rd_data_b_i;
+      OpBSelRegister:  alu_base_operation_o.operand_b = rf_base_rd_data_b_i;
+      OpBSelImmediate: alu_base_operation_o.operand_b = insn_dec_base_i.i;
+      default:         alu_base_operation_o.operand_b = rf_base_rd_data_b_i;
     endcase
   end
 
@@ -301,18 +294,12 @@
 
   always_comb begin
     unique case (insn_dec_base_i.rf_wdata_sel)
-      RfWdSelEx:
-        rf_base_wr_data_o = alu_base_operation_result_i;
-      RfWdSelLsu:
-        rf_base_wr_data_o = lsu_base_rdata_i;
-      RfWdSelNextPc:
-        rf_base_wr_data_o = {{(32-ImemAddrWidth){1'b0}}, next_insn_addr};
-      RfWdSelIspr:
-        rf_base_wr_data_o = csr_rdata;
-      RfWdSelIncr:
-        rf_base_wr_data_o = increment_out;
-      default:
-        rf_base_wr_data_o = alu_base_operation_result_i;
+      RfWdSelEx:     rf_base_wr_data_o = alu_base_operation_result_i;
+      RfWdSelLsu:    rf_base_wr_data_o = lsu_base_rdata_i;
+      RfWdSelNextPc: rf_base_wr_data_o = {{(32-ImemAddrWidth){1'b0}}, next_insn_addr};
+      RfWdSelIspr:   rf_base_wr_data_o = csr_rdata;
+      RfWdSelIncr:   rf_base_wr_data_o = increment_out;
+      default:       rf_base_wr_data_o = alu_base_operation_result_i;
     endcase
   end
 
@@ -327,12 +314,9 @@
   // Base ALU Operand B MUX
   always_comb begin
     unique case (insn_dec_bignum_i.op_b_sel)
-      OpBSelRegister:
-        alu_bignum_operation_o.operand_b = rf_bignum_rd_data_b_i;
-      OpBSelImmediate:
-        alu_bignum_operation_o.operand_b = insn_dec_bignum_i.i;
-      default:
-        alu_bignum_operation_o.operand_b = rf_bignum_rd_data_b_i;
+      OpBSelRegister:  alu_bignum_operation_o.operand_b = rf_bignum_rd_data_b_i;
+      OpBSelImmediate: alu_bignum_operation_o.operand_b = insn_dec_bignum_i.i;
+      default:         alu_bignum_operation_o.operand_b = rf_bignum_rd_data_b_i;
     endcase
   end
 
@@ -353,14 +337,10 @@
 
   always_comb begin
     unique case (insn_dec_bignum_i.rf_wdata_sel)
-      RfWdSelEx:
-        rf_bignum_wr_data_o = alu_bignum_operation_result_i;
-      RfWdSelLsu:
-        rf_bignum_wr_data_o = lsu_bignum_rdata_i;
-      RfWdSelIspr:
-        rf_bignum_wr_data_o = ispr_rdata_i;
-      default:
-        rf_bignum_wr_data_o = alu_bignum_operation_result_i;
+      RfWdSelEx:   rf_bignum_wr_data_o = alu_bignum_operation_result_i;
+      RfWdSelLsu:  rf_bignum_wr_data_o = lsu_bignum_rdata_i;
+      RfWdSelIspr: rf_bignum_wr_data_o = ispr_rdata_i;
+      default:     rf_bignum_wr_data_o = alu_bignum_operation_result_i;
     endcase
   end