[top] Correct parameter defaults in top_earlgrey
Address #6366
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 40e7f69..0694204 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -3295,12 +3295,15 @@
rst_otp_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
+ param_decl:
+ {
+ InstrExec: "0"
+ }
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_infra
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra
}
- param_decl: {}
memory: {}
param_list:
[
@@ -3338,7 +3341,7 @@
name: InstrExec
desc: Support execution from SRAM
type: bit
- default: "1"
+ default: "0"
expose: "true"
name_top: SramCtrlRetAonInstrExec
}
@@ -3971,13 +3974,19 @@
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
+ param_decl:
+ {
+ Masking: "1"
+ SBoxImpl: aes_pkg::SBoxImplDom
+ SecStartTriggerDelay: "0"
+ SecAllowForcingMasks: 1'b0
+ }
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_aes
clk_edn_i: clkmgr_aon_clocks.clk_main_aes
}
domain: "0"
- param_decl: {}
memory: {}
param_list:
[
@@ -3997,7 +4006,7 @@
Masking requires the use of a masked S-Box, see SBoxImpl parameter.
'''
type: bit
- default: 1'b1
+ default: "1"
expose: "true"
name_top: AesMasking
}
@@ -4213,6 +4222,7 @@
param_decl:
{
EnMasking: "1"
+ ReuseShare: "0"
}
clock_srcs:
{
@@ -5103,13 +5113,16 @@
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
rst_otp_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
}
+ param_decl:
+ {
+ InstrExec: "1"
+ }
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
- param_decl: {}
memory: {}
param_list:
[
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index c078c84..f52620c 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -444,6 +444,9 @@
clock_group: "infra",
reset_connections: {rst_ni: "sys_io_div4", rst_otp_ni: "lc_io_div4"},
domain: "Aon",
+ param_decl: {
+ InstrExec: "0",
+ }
base_addr: "0x40500000"
},
{ name: "flash_ctrl",
@@ -475,6 +478,13 @@
clock_srcs: {clk_i: "main", clk_edn_i: "main"},
clock_group: "trans",
reset_connections: {rst_ni: "sys", rst_edn_ni: "sys"},
+ param_decl: {
+ Masking: "1",
+ SBoxImpl: "aes_pkg::SBoxImplDom",
+ SecStartTriggerDelay: "0",
+ SecAllowForcingMasks: "1'b0",
+
+ }
base_addr: "0x41100000",
},
{ name: "hmac",
@@ -486,7 +496,10 @@
},
{ name: "kmac",
type: "kmac",
- param_decl: {EnMasking: "1"}
+ param_decl: {
+ EnMasking: "1",
+ ReuseShare: "0"
+ }
clock_srcs: {clk_i: "main", clk_edn_i: "main"}
clock_group: "trans"
reset_connections: {rst_ni: "sys", rst_edn_ni: "sys"}
@@ -534,6 +547,9 @@
clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"},
clock_group: "secure",
reset_connections: {rst_ni: "sys", rst_otp_ni: "lc_io_div4"},
+ param_decl: {
+ InstrExec: "1",
+ }
base_addr: "0x411C0000",
},
{ name: "otbn",
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
index 48cf277..4a5444c 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
@@ -1073,13 +1073,6 @@
//////////////////////
top_earlgrey #(
- .AesMasking(1'b1),
- .AesSBoxImpl(aes_pkg::SBoxImplDom),
- .SecAesStartTriggerDelay(0),
- .SecAesAllowForcingMasks(1'b0),
- .KmacReuseShare(0),
- .SramCtrlRetAonInstrExec(0),
- .SramCtrlMainInstrExec(1),
.PinmuxAonTargetCfg(PinmuxTargetCfg)
) top_earlgrey (
.rst_ni ( aon_pok ),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index a3b8463..3ce4eb7 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -42,13 +42,13 @@
// parameters for aon_timer_aon
// parameters for sensor_ctrl_aon
// parameters for sram_ctrl_ret_aon
- parameter bit SramCtrlRetAonInstrExec = 1,
+ parameter bit SramCtrlRetAonInstrExec = 0,
// parameters for flash_ctrl
// parameters for rv_dm
parameter logic [31:0] RvDmIdcodeValue = 32'h 0000_0001,
// parameters for rv_plic
// parameters for aes
- parameter bit AesMasking = 1'b1,
+ parameter bit AesMasking = 1,
parameter aes_pkg::sbox_impl_e AesSBoxImpl = aes_pkg::SBoxImplDom,
parameter int unsigned SecAesStartTriggerDelay = 0,
parameter bit SecAesAllowForcingMasks = 1'b0,
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index 73d93b8..f493b5b 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -927,13 +927,6 @@
//////////////////////
top_${top["name"]} #(
- .AesMasking(1'b1),
- .AesSBoxImpl(aes_pkg::SBoxImplDom),
- .SecAesStartTriggerDelay(0),
- .SecAesAllowForcingMasks(1'b0),
- .KmacReuseShare(0),
- .SramCtrlRetAonInstrExec(0),
- .SramCtrlMainInstrExec(1),
.PinmuxAonTargetCfg(PinmuxTargetCfg)
) top_${top["name"]} (
.rst_ni ( aon_pok ),
