| commit | 9d48c08377e43fef04f79847ef402ea364a1f15d | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Sun May 16 16:06:32 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Tue May 25 09:48:23 2021 +0100 |
| tree | 4f41c1be7e0279c08470be5ad44273549970855c | |
| parent | 500b0f09b9fe7df8e433bc2bfd888a8e3ab073ad [diff] |
[otbn,dv] Monitor the trace interface directly; connect to coverage This commit adds otbn_trace_monitor, a UVM monitor that snoops on the RTL trace interface. This passes transactions to the scoreboard, which already received the equivalent transactions from the ISS. The scoreboard then pairs them up again and passes them to otbn_env_cov to be used for coverage checking. This patch adds the infrastructure that you need in order to cross executed instruction mnemonics (from the ISS) with instruction data (from the RTL). It doesn't add any new coverage points, but it does add a cross-check to make sure that the instruction addresses from the ISS and RTL match. Note: This isn't part of the verification of the block, as such, but is needed to make sure that we are collecting the coverage that we think we're collecting. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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