[lint/dv] Create lint targets for testbench environments
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/aes/dv/aes_sim.core b/hw/ip/aes/dv/aes_sim.core
index 949b1bb..027a05d 100644
--- a/hw/ip/aes/dv/aes_sim.core
+++ b/hw/ip/aes/dv/aes_sim.core
@@ -18,9 +18,21 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/ip/alert_handler/dv/alert_handler_generic_sim.core b/hw/ip/alert_handler/dv/alert_handler_generic_sim.core
index bfa1132..5fa87fd 100644
--- a/hw/ip/alert_handler/dv/alert_handler_generic_sim.core
+++ b/hw/ip/alert_handler/dv/alert_handler_generic_sim.core
@@ -26,7 +26,7 @@
ip_hjson: ../data/alert_handler.hjson
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
@@ -34,3 +34,15 @@
generate:
- ral
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/ip/entropy_src/dv/entropy_src_sim.core b/hw/ip/entropy_src/dv/entropy_src_sim.core
index 262cb4a..e83f5af 100644
--- a/hw/ip/entropy_src/dv/entropy_src_sim.core
+++ b/hw/ip/entropy_src/dv/entropy_src_sim.core
@@ -18,9 +18,21 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/ip/flash_ctrl/dv/flash_ctrl_sim.core b/hw/ip/flash_ctrl/dv/flash_ctrl_sim.core
index dc2f017..83a2c5d 100644
--- a/hw/ip/flash_ctrl/dv/flash_ctrl_sim.core
+++ b/hw/ip/flash_ctrl/dv/flash_ctrl_sim.core
@@ -24,9 +24,21 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/ip/gpio/dv/gpio_sim.core b/hw/ip/gpio/dv/gpio_sim.core
index 3240490..96efbeb 100644
--- a/hw/ip/gpio/dv/gpio_sim.core
+++ b/hw/ip/gpio/dv/gpio_sim.core
@@ -18,9 +18,22 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
diff --git a/hw/ip/hmac/dv/hmac_sim.core b/hw/ip/hmac/dv/hmac_sim.core
index 456b25e..77f8c9b 100644
--- a/hw/ip/hmac/dv/hmac_sim.core
+++ b/hw/ip/hmac/dv/hmac_sim.core
@@ -18,9 +18,22 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
diff --git a/hw/ip/i2c/dv/i2c_sim.core b/hw/ip/i2c/dv/i2c_sim.core
index 9a268ec..7e58574 100644
--- a/hw/ip/i2c/dv/i2c_sim.core
+++ b/hw/ip/i2c/dv/i2c_sim.core
@@ -18,9 +18,21 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/ip/rv_timer/dv/rv_timer_sim.core b/hw/ip/rv_timer/dv/rv_timer_sim.core
index e6ccd36..e8c1ed7 100644
--- a/hw/ip/rv_timer/dv/rv_timer_sim.core
+++ b/hw/ip/rv_timer/dv/rv_timer_sim.core
@@ -18,9 +18,22 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
diff --git a/hw/ip/spi_device/dv/spi_device_sim.core b/hw/ip/spi_device/dv/spi_device_sim.core
index 74d7520..06fe73e 100644
--- a/hw/ip/spi_device/dv/spi_device_sim.core
+++ b/hw/ip/spi_device/dv/spi_device_sim.core
@@ -18,9 +18,21 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/ip/trial1/dv/trial1_sim.core b/hw/ip/trial1/dv/trial1_sim.core
index 6f0d8bc..a3d5c51 100644
--- a/hw/ip/trial1/dv/trial1_sim.core
+++ b/hw/ip/trial1/dv/trial1_sim.core
@@ -23,9 +23,22 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
diff --git a/hw/ip/uart/dv/uart_sim.core b/hw/ip/uart/dv/uart_sim.core
index ee802f5..7e10a64 100644
--- a/hw/ip/uart/dv/uart_sim.core
+++ b/hw/ip/uart/dv/uart_sim.core
@@ -18,9 +18,21 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/ip/usbdev/dv/usbdev_sim.core b/hw/ip/usbdev/dv/usbdev_sim.core
index 7969b99..d731896 100644
--- a/hw/ip/usbdev/dv/usbdev_sim.core
+++ b/hw/ip/usbdev/dv/usbdev_sim.core
@@ -18,9 +18,21 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core
index 5f4d9c8..908d2b3 100644
--- a/hw/top_earlgrey/dv/chip_sim.core
+++ b/hw/top_earlgrey/dv/chip_sim.core
@@ -24,11 +24,23 @@
- tb/tb.sv
file_type: systemVerilogSource
-
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
diff --git a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_sim.core b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_sim.core
index 20c7f8e..652fe25 100644
--- a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_sim.core
+++ b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_sim.core
@@ -27,7 +27,7 @@
ip_hjson: ../data/autogen/alert_handler.hjson
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
@@ -35,3 +35,16 @@
generate:
- ral
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim.core b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim.core
index f011f57..0495114 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim.core
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim.core
@@ -20,8 +20,21 @@
targets:
- sim:
+ sim: &sim_target
toplevel: xbar_tb_top
filesets:
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim.core b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim.core
index 53240b0..e024c0a 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim.core
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim.core
@@ -20,8 +20,21 @@
targets:
- sim:
+ sim: &sim_target
toplevel: xbar_tb_top
filesets:
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
diff --git a/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson
new file mode 100644
index 0000000..525f40e
--- /dev/null
+++ b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson
@@ -0,0 +1,90 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+
+ // This is the primary cfg hjson for DV linting. It imports ALL individual lint
+ // cfgs of the IPs DV environments and the full chip DV environment for top_earlgrey.
+ // This enables to run them all as a regression in one shot.
+ name: top_earlgrey_dv_batch
+
+ import_cfgs: [// common server configuration for results upload
+ "{proj_root}/hw/data/common_project_cfg.hjson"
+ // tool-specific configuration
+ "{proj_root}/hw/lint/data/{tool}.hjson"]
+
+ // Different dashboard output path for each tool
+ rel_path: "hw/top_earlgrey/dv/lint/{tool}"
+
+ use_cfgs: [{ name: aes
+ fusesoc_core: lowrisc:dv:aes_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/aes/dv/lint/{tool}"
+ },
+ { name: alert_handler
+ fusesoc_core: lowrisc:dv:alert_handler_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/top_earlgrey/ip/alert_handler/dv/lint/{tool}"
+ },
+ { name: entropy_src
+ fusesoc_core: lowrisc:dv:entropy_src_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/entropy_src/dv/lint/{tool}"
+ },
+ { name: flash_ctrl
+ fusesoc_core: lowrisc:dv:flash_ctrl_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/flash_ctrl/dv/lint/{tool}"
+ },
+ { name: gpio
+ fusesoc_core: lowrisc:dv:gpio_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/gpio/dv/lint/{tool}"
+ },
+ { name: hmac
+ fusesoc_core: lowrisc:dv:hmac_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/hmac/dv/lint/{tool}"
+ },
+ { name: i2c
+ fusesoc_core: lowrisc:dv:i2c_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/i2c/dv/lint/{tool}"
+ },
+ { name: rv_timer
+ fusesoc_core: lowrisc:dv:rv_timer_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/rv_timer/dv/lint/{tool}"
+ },
+ { name: spi_device
+ fusesoc_core: lowrisc:dv:spi_device_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/spi_device/dv/lint/{tool}"
+ },
+ { name: uart
+ fusesoc_core: lowrisc:dv:uart_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/uart/dv/lint/{tool}"
+ },
+ { name: usbdev
+ fusesoc_core: lowrisc:dv:usbdev_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/usbdev/dv/lint/{tool}"
+ },
+ { name: xbar_main
+ fusesoc_core: lowrisc:dv:xbar_main_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/top_earlgrey/ip/xbar_main/dv/lint/{tool}"
+ },
+ { name: xbar_peri
+ fusesoc_core: lowrisc:dv:xbar_peri_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/top_earlgrey/ip/xbar_peri/dv/lint/{tool}"
+ },
+ { name: chip
+ fusesoc_core: lowrisc:dv:chip_sim
+ import_cfgs: ["{proj_root}/hw/lint/data/common_lint_cfg.hjson"]
+ rel_path: "hw/top_earlgrey/dv/lint/{tool}"
+ },
+ ]
+}
diff --git a/util/tlgen/xbar.sim.core.tpl b/util/tlgen/xbar.sim.core.tpl
index d027786..55ee809 100644
--- a/util/tlgen/xbar.sim.core.tpl
+++ b/util/tlgen/xbar.sim.core.tpl
@@ -20,8 +20,21 @@
targets:
- sim:
+ sim: &sim_target
toplevel: xbar_tb_top
filesets:
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
+
