[entropy_src/dv] Support complete backpressure
Testing the cs_aes_halt_req/ack port calls for improving backpressure
support in the entire entropy_src pipeline, as submitted in PR #14644.
These changes in turn actually simplify some of the timing subtleties
that have to be done in the DV scoreboard. Some of the DV timing
hacks done prior to this commit no longer accurately predict
the timing of the entropy source. Most notably, data samples
no longer linger in the RNG bit-select FIFO until another RNG
sample is recieved.
This commit also updates the assertion tweaks that need to be
done to support the backpressure changes. This is because
there is another instance of prim_mubi4_sync that needs to be
relaxed when bad Mubi values are injected into the pipeline.
Signed-off-by: Martin Lueker-Boden <martin.lueker-boden@wdc.com>
diff --git a/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv b/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
index f3e9bcb..83bdbfa 100644
--- a/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
+++ b/hw/ip/entropy_src/dv/env/entropy_src_scoreboard.sv
@@ -1386,7 +1386,6 @@
begin
bit rng_bit_enable = (`gmv(ral.conf.rng_bit_enable) == MuBi4True);
int rng_shutdown_dly = base_shutdown_dly;
- rng_shutdown_dly += rng_bit_enable ? 1 : 0;
cfg.clk_rst_vif.wait_clks(rng_shutdown_dly);
dut_pipeline_enabled = 0;
end
@@ -1875,35 +1874,6 @@
val = rng_item.h_data;
end
end : rng_loop
- if (bit_sel_enable) begin
- // Timing Detail:
- // In bit select mode, the DUT won't process the data until an extra RNG sample is accepted.
- // If a disable event happens before the following sample is received, everything is cleared.
- // To mimic this behavior, this task maintains control until at least one more sample is
- // present in the rng_fifo.
- if (dut_pipeline_enabled) begin
- fork : isolation_fork
- begin
- fork
- // Exploit the fact that peek is a blocking task to check the rng_fifo depth without
- // modifying it.
- // Note that the alternate approach: wait(!rng_fifo.is_empty()) does not work with VCS
- rng_fifo.peek(rng_item);
- begin
- wait(!dut_pipeline_enabled);
- `uvm_info(`gfn, "Disable detected (Waiting B)", UVM_MEDIUM);
- end
- join_any
- disable fork;
- end
- join : isolation_fork
- end else begin
- `uvm_info(`gfn, "Disable detected (Pre bit_sel_enable wait)", UVM_FULL);
- end
- if (!dut_pipeline_enabled && rng_fifo.is_empty()) begin
- disable_detected = 1;
- end
- end
endtask
task collect_entropy();
diff --git a/hw/ip/entropy_src/dv/sva/entropy_src_assert_if.sv b/hw/ip/entropy_src/dv/sva/entropy_src_assert_if.sv
index 88f1447..9e323c7 100644
--- a/hw/ip/entropy_src/dv/sva/entropy_src_assert_if.sv
+++ b/hw/ip/entropy_src/dv/sva/entropy_src_assert_if.sv
@@ -23,6 +23,8 @@
tb.dut.u_entropy_src_core.u_prim_mubi4_sync_es_type
`define PATH9 \
tb.dut.u_entropy_src_core.u_prim_mubi4_sync_es_enable
+`define PATH10 \
+ tb.dut.u_entropy_src_core.u_prim_mubi4_sync_es_prebitsel_enable
`define CORE \
tb.dut.u_entropy_src_core
`define SHA3 \
@@ -73,6 +75,10 @@
$assertoff(0, `PATH9.PrimMubi4SyncCheckTransients_A);
$assertoff(0, `PATH9.PrimMubi4SyncCheckTransients0_A);
$assertoff(0, `PATH9.PrimMubi4SyncCheckTransients1_A);
+
+ $assertoff(0, `PATH10.PrimMubi4SyncCheckTransients_A);
+ $assertoff(0, `PATH10.PrimMubi4SyncCheckTransients0_A);
+ $assertoff(0, `PATH10.PrimMubi4SyncCheckTransients1_A);
endtask // assert_off_alert
task automatic assert_on_alert ();
@@ -111,6 +117,10 @@
$asserton(0, `PATH9.PrimMubi4SyncCheckTransients_A);
$asserton(0, `PATH9.PrimMubi4SyncCheckTransients0_A);
$asserton(0, `PATH9.PrimMubi4SyncCheckTransients1_A);
+
+ $asserton(0, `PATH10.PrimMubi4SyncCheckTransients_A);
+ $asserton(0, `PATH10.PrimMubi4SyncCheckTransients0_A);
+ $asserton(0, `PATH10.PrimMubi4SyncCheckTransients1_A);
endtask // assert_on_alert
task automatic assert_off_err ();
