[prim_xilinx_flop] Add a Xilinx version with keep attribute
This adds a prim_xilinx_flop.sv variant that places a keep attribute on
the flop output in order to prevent Vivado from optimizing the flop
away.
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/prim_xilinx/prim_xilinx_flop.core b/hw/ip/prim_xilinx/prim_xilinx_flop.core
new file mode 100644
index 0000000..ecd876b
--- /dev/null
+++ b/hw/ip/prim_xilinx/prim_xilinx_flop.core
@@ -0,0 +1,40 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_xilinx:flop"
+description: "generic flop"
+filesets:
+ files_rtl:
+ files:
+ - rtl/prim_xilinx_flop.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+
+targets:
+ default:
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv
new file mode 100644
index 0000000..f98314a
--- /dev/null
+++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv
@@ -0,0 +1,27 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`include "prim_assert.sv"
+
+module prim_xilinx_flop # (
+ parameter int Width = 1,
+ localparam int WidthSubOne = Width-1,
+ parameter logic [WidthSubOne:0] ResetValue = 0
+) (
+ input clk_i,
+ input rst_ni,
+ input [Width-1:0] d_i,
+ // Prevent Vivado from optimizing this signal away.
+ (* keep = "true" *) output logic [Width-1:0] q_o
+);
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ q_o <= ResetValue;
+ end else begin
+ q_o <= d_i;
+ end
+ end
+
+endmodule // prim_xilinx_flop
